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US 9,805,827 B2Granted
Semiconductor memory devices, memory systems including the same and methods of operating the same
AssigneeSamsung Electronics Co., Ltd.
InventorsJong-Pil Son, Chul-Woo Park, Hoi-Ju Chung, Sang-Uhn Cha, Seong-Jin Jang
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Abstract
A semiconductor memory device includes a memory cell array and a test circuit. The test circuit reads data stream from the memory cell array, configured to, on comparing bits of each first unit in the data stream, compares corresponding bits in the first units as each second unit and outputs a fail information signal including pass/fail information on the data stream and additional information on the data stream, in a test mode of the semiconductor memory device.
Claims20
A semiconductor memory device comprising:
- a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells connected to intersections of word-lines and bit-lines;
- an input/output (I/O) gating circuit connected between the memory cell array and data lines;
- and
- a test circuit connected to the I/O gating circuit through the data lines, and configured to:
- read out a data stream from the memory cell array, wherein the data stream includes a plurality of first bits output from the plurality of memory blocks and received from the data lines, first units of bits of the plurality of first bits each first unit comprising bits output only from a corresponding memory block, and second units of bits of the plurality of first bits each second unit comprising a corresponding bit of each of the first units of bits, each second unit of bits being received from a different memory block of the plurality of memory blocks;
- perform a plurality of first comparisons, each first comparison comprising a comparison of all bits of a corresponding first unit in the data stream;
- store a first result signal as a result of the plurality of the first comparisons;
- perform a plurality of second comparisons, each second comparison comprising a comparison of all bits of a corresponding second unit, the all bits of a corresponding second unit being received from a different memory block of the plurality of memory blocks;
- store a second result signal as a result of the plurality of the second comparisons;
- and
- output a fail information signal including pass/fail information on the data stream and additional information on the data stream to outside the semiconductor memory device based on the first result signal and the second result signal during a test mode of the semiconductor memory device.
8 more elements
A memory system comprising:
- a semiconductor memory device;
- and
- a test device configured to test the semiconductor memory device,
- wherein the semiconductor memory device comprises:
- a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells connected to intersections of word-lines and bit-lines;
- and
- a test circuit configured to read a data stream from the memory cell array, the data stream including bits of a plurality of first units, the test circuit configured to compare bits of each first unit of the plurality of first units in the data stream, compare corresponding bits in the plurality of first units as each second unit, which are bits of the each second unit of the plurality of first units, and configured to output a fail information signal including pass/fail information on the data stream and additional information on the data stream, in a test mode of the semiconductor memory device,
- wherein each bit of the bits of the each first unit is output from the same memory block of the plurality of memory blocks, and
- wherein each bit of the bits of the each second unit is output from a different memory block of the plurality of memory blocks.
6 more elements
A method of operating a semiconductor memory device including a memory cell array having a plurality of memory blocks, the method comprising:
- reading test pattern data from the memory cell array in a codeword basis, in a test mode of the semiconductor memory device, wherein the test pattern data includes bits of a plurality of first units;
- comparing bits of each first unit of the plurality of first units in the test pattern data to output a first result signal;
- comparing corresponding bits in the plurality of first units as each second unit, which are bits of the each second unit of the plurality of first units, to output a second result signal;
- storing the first result signal and the second result signal in a first region and a second region of a fail address memory respectively;
- and
- repairing fail cells by one of an error correction code (ECC) operation and a redundancy repair operation based on a number of the fail cells, included in an access address, by referring to the fail address memory, in a normal mode of the semiconductor memory device,
- wherein each bit of the comparing bits of the each first unit is output from the same memory block of the plurality of memory blocks, and
- wherein each bit of the comparing bits of the each second unit is output from a different memory block of the plurality of memory blocks.
5 more elements
Dependencies are inferred from the claim text.