Method and apparatus for testing integrated circuit
AssigneeNXP USA, Inc.
InventorsWeiwei Sang, Wanggen Zhang
Life of this patent
Estimating the term…
Abstract
An integrated circuit (IC) having a memory for storing data also has a memory built in self-test (MBIST) unit coupled to the memory for testing an operation of the memory. A test interface provides test data. Flip-flops of the IC are connected together into at least one serial scan chain. The test interface unit receives test data including MBIST configuration data. The MBIST unit, in a first mode, tests the memory based on the MBIST configuration data at least partly in parallel with a scan test using the scan chain. Thus, both the memory and the logic circuitry can be tested in parallel.
Claims18
An integrated circuit, comprising:
- a memory for storing data;
- a memory built in self-test (MBIST) unit coupled to the memory for testing an operation of the memory;
- a test interface unit coupled to the MBIST unit for communicating test data to the MBIST unit;
- and
- a plurality of flip-flops connected together into at least one serial scan chain;
- wherein the test interface unit is arranged to receive test data comprising MBIST configuration data,
- wherein the MBIST unit is arranged, in a first mode, to perform a test of the memory based upon the MBIST configuration data at least partly in parallel with a scan test using the at least one scan chain,
- wherein the plurality of flip-flops and the MBIST unit both receive scan data in from a scan input of the integrated circuit, and
- wherein the test interface unit comprises an interface that conforms to IEEE Standard 1149.1 1990.
A method of testing operation of an integrated circuit, the method comprising:
- receiving, at a test interface unit of the integrated circuit, test data comprising memory built-in self-test (MBIST) configuration data, wherein the test interface unit comprises an interface that conforms to IEEE Standard 1149.1 1990;
- configuring a MBIST unit of the integrated circuit according to the MBIST configuration data, wherein the MBIST unit is arranged to test a memory of the integrated circuit;
- loading a serial scan chain of flip-flops with scan data for performing a scan test of a portion of the integrated circuit;
- and
- performing, in a first test mode of the integrated circuit, the scan test at least partly in parallel with the MBIST unit testing the memory,
- wherein the serial scan chain of flip-flops and the MBIST unit both receive scan data in from a scan input of the integrated circuit.
An integrated circuit, comprising:
- a memory for storing data;
- a memory built in self-test (MBIST) unit coupled to the memory for testing an operation of the memory;
- a test interface unit for communicating test data to the MBIST unit, wherein the test interface unit comprises an interface that complies with IEEE Standard 1149.1 1990;
- and
- a plurality of flip-flops connected together into at least one serial scan chain;
- wherein the MBIST unit is arranged, in a first mode, to perform a test of the memory at least partly simultaneously with a scan test using the at least one scan chain and, in a second test mode, a plurality of flip-flops of the MBIST unit are arranged to form at least one serial scan chain of the scan test, and wherein the serial scan chain and the MBIST unit both receive scan data in from a scan input of the integrated circuit.
Dependencies are inferred from the claim text.