Memory error capture logic
AssigneeApple Inc.
InventorPreminder Singh
Life of this patent
Estimating the term…
Abstract
A built-in self test (BIST) may be performed on a device memory having two memory portions that are symmetrical (e.g., two symmetric halves of the device memory). The BIST may be run on the first memory portion. Error logic output from the first memory portion is captured (stored) in the second memory portion during the BIST run process. Error logic output from the first memory portion may include error data and an address of the memory error in the first memory portion. As the first and second memory portions are symmetric, the memory errors captured (stored) in the second memory portion are located at identical locations to the location of the memory errors in the first memory portion. A memory dump from the second memory portion after the BIST may provide a map of the memory errors in the first memory portion.
Claims20
A method, comprising:
- performing a memory error test on a single memory, wherein the single memory comprises a first memory portion and a second memory portion, the first memory portion and the second memory portion being symmetric, and wherein the memory error test is performed on the first memory portion of the single memory, the memory error test comprising a built-in self test in the single memory;
- providing error logic output from the first memory portion to the second memory portion of the memory in response to a memory error instance in the first memory portion, wherein the error logic output comprises an error flag and error data, the error data including an address of a first location of the memory error in the first memory portion;
- storing the error data from the first memory portion in the second memory portion using the address from the error data as an address of a second location of the stored error data in the second memory portion, whereby the second location in the second memory portion at which the error data is stored is identical to the first location of the memory error in the first memory portion;
- and
- performing a memory dump from the second memory portion, wherein the memory dump comprises a map of memory errors in the first memory portion.
A device, comprising:
- a memory separated into at least a first memory portion and a second memory portion, wherein the first memory portion and the second memory portion are symmetrical;
- and
- a logic circuit configured to perform a memory error test on the first memory portion, wherein the memory error test comprises a built-in self test in the memory;
- wherein the logic circuit is configured to provide error logic output from the first memory portion to the second memory portion in response to a memory error instance in the first memory portion during the memory error test, wherein the error logic output comprises an error flag and error data, the error data including an address of a first location of the memory error in the first memory portion;
- wherein the logic circuit is configured to store the error data from the first memory portion in the second memory portion using the address from the error data as an address of a second location of the stored error data in the second memory portion, whereby the second location in the second memory portion at which the error data is stored is identical to the first location of the memory error in the first memory portion;
- and
- wherein the logic circuit is configured to run the memory error test on the second memory portion and provide error logic output from the second memory portion to the first memory portion in response to a memory error instance in the second memory portion during the memory error test.
A non-transient computer-readable medium including instructions that, when executed by one or more processors, causes the one or more processors to perform a method, comprising:
- performing a memory error test on a single memory, wherein the single memory comprises a first memory portion and a second memory portion, the first memory portion and the second memory portion being symmetric, and wherein the memory error test is performed on the first memory portion of the single memory, the memory error test comprising a built-in self test in the single memory;
- receiving error logic output from the first memory portion in response to a memory error instance in the first memory portion, wherein the error logic output comprises an error flag and error data, the error data including an address of a first location of the memory error in the first memory portion;
- generating a write enable signal and write data signal for the second memory portion from the error logic output, wherein the write data signal comprises error data from the first memory portion;
- providing the write enable signal and the write data signal to the second memory portion;
- storing the error data from the first memory portion in the second memory portion using the address from the error data as an address of a second location of the stored error data in the second memory portion, whereby the second location in the second memory portion at which the error data is stored is identical to the first location of the memory error in the first memory portion;
- and
- performing a memory dump from the second memory portion, wherein the memory dump comprises a map of memory errors in the first memory portion.
Dependencies are inferred from the claim text.