Semiconductor memory device and test method therefor
AssigneeRenesas Electronics Corporation
InventorsShinji Tanaka, Yuichiro Ishii, Masaki Tsukude, Yoshikazu Saito
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Abstract
A semiconductor memory device includes a memory array including a plurality of memory cells arranged in a matrix form, a plurality of bit line pairs disposed in the columns of the memory cells, a plurality of word lines disposed in the rows of the memory cells, a write drive circuit adapted to transfer data to a bit line pair in a selected column in accordance with write data, and a control circuit that deselects the word lines during a test and drives a low-potential side bit line of the bit line pair in the selected column to a negative voltage level in accordance with the potentials of bit lines in the selected column.
Claims20
A semiconductor memory device comprising:
- a memory array that includes a plurality of memory cells arranged in a matrix form;
- a plurality of bit line pairs that are disposed in the columns of the memory cells;
- a plurality of word lines that are disposed in the rows of the memory cells;
- a write drive circuit that transfers data to a bit line pair in a selected column in accordance with write data;
- and
- a control circuit that deselects the word lines during a test and drives a low-potential side bit line of the bit line pair in the selected column to a negative voltage level in accordance with the potentials of bit lines in the selected column.
A test method for a semiconductor memory device having a plurality of memory cells arranged in a matrix form, the test method comprising:
- writing, by a write drive circuit, first data into a plurality of memory cells;
- while a plurality of word lines disposed in the columns of the memory cells are deselected, driving, by a control circuit, the low-potential side bit line of a bit line pair in the selected column, which is among a plurality of bit line pairs disposed in the columns of the memory cells, to a negative voltage level in accordance with second data complementary to the first data;
- and
- reading the data written into the memory cells.
A semiconductor memory device comprising:
- a memory array that includes a plurality of memory cells;
- a plurality of bit line pairs that are disposed in the columns of the memory cells, a bit line pair from among the plurality of bit line pairs receiving data in a selected column in accordance with write data;
- a plurality of word lines that are disposed in the rows of the memory cells;
- and
- a control circuit that deselects the word lines during a test and drives a low-potential side bit line of the bit line pair in the selected column to a negative voltage level in accordance with the potentials of bit lines in the selected column.
Dependencies are inferred from the claim text.