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US 9,805,818 B2Granted
Fuse memory having discharge circuit
AssigneeSamsung Electronics Co., Ltd.
InventorsTae-seong Kim, Cheol-ha Lee
Life of this patent
Estimating the term…
Abstract
A fuse memory comprising a discharge circuit is provided. The fuse memory includes a fuse cell array comprising fuse cells connected to read word lines, programs word lines, and bit lines arranged in rows and columns; and at least one discharge circuit arranged in each of the rows. The discharge circuit discharges a voltage level of a program word line of the fuse cells selected in a read mode to a ground voltage.
Claims19
A fuse memory comprising:
- a fuse cell array including fuse cells in rows and columns of the fuse cell array, each of the rows connected to a read word line and a programmed word line, and each of the columns connected to a bit line, each of the fuse cells including,
- a fuse device including a first terminal configured to receive a program voltage,
- a read transistor between a second terminal of the fuse device and the bit line of a respective one of the columns, the read transistor including a gate connected to the read word line of a respective one of the rows, and
- a program transistor between the second terminal of the fuse device and a ground voltage source, the program transistor including a gate connected to the programmed word line of the respective one of the rows;
- and
- at least one discharge circuit in each of the rows of the fuse cell array, the at least one discharge circuit configured to turn off the program transistor of one of the fuse cells, when the fuse cell is read.
3 more elements
A fuse memory comprising:
- a fuse cell array including,
- fuse cells connected to read word lines, program word lines, and bit lines, the read word lines and the program word lines being in rows of the fuse cell array, and the bit lines being in columns of the fuse cell array, each of the fuse cells including a fuse device, and
- a discharge circuit connected to the read word lines and the program word lines in each of the rows, the discharge circuit configured to discharge a voltage level of a selected one of the program word lines of the fuse cells to a ground voltage by maintaining a program transistor having a gate connected to the selected one of the program word lines in an open state, when the fuse memory is operating in a read mode;
- a word line driver configured to selectively drive one of the read word lines and the program word lines of a selected one of the rows based on an operation mode;
- and
- a sense amplifier configured to generate a sensing output signal by sensing and amplifying data output from the fuse cells to the bit lines.
3 more elements
A fuse memory comprising:
- at least one fuse cell including a fuse device having a first terminal and a second terminal, the first terminal connected in parallel between a read transistor and a program transistor, and the second terminal configured to receive a program voltage;
- and
- at least one discharge circuit configured to disconnect the first terminal from a ground voltage source by maintaining the program transistor in an open state, when the fuse memory is operating in a read mode.
Dependencies are inferred from the claim text.