Implementation of a one time programmable memory using a MRAM stack design

A magnetic one-time-programmable memory array comprising:

• a plurality of magnetic one-time-programmable memory cells arranged in rows and columns, each magnetic one-time-programmable memory cell comprising:
• a magnetic tunnel junction (MTJ) device comprising a fixed magnetic layer fabricated on a first electrode, a tunnel barrier insulating layer fabricated upon the fixed magnetic layer, a free magnetic layer fabricated on the tunnel barrier insulating layer, and a second electrode fabricated on the free magnetic layer, wherein a diameter of the MTJ device is chosen such that the tunnel barrier insulating layer is broken down by a program voltage applied across the magnetic one-time-programmable memory cell that is approximately equal to a write voltage for a read/write MRAM memory cell having an equal tunnel barrier insulating layer thickness;
• and
• a gating metal oxide semiconductor (MOS) transistor serially connected to the MTJ device;
• a plurality of pairs of bit lines wherein a first bit line of the pairs of bit lines is connected to the second electrode of the MTJ device of the magnetic one-time-programmable memory cells of an associated column of the array, a second bit line of the pairs of bit lines is connected to the source of the gating MOS transistor of the magnetic one-time-programmable memory cells of the associated column of the array;
• a plurality of word lines wherein each word line is associated with each row of the plurality of magnetic one-time-programmable memory cells such that the gates of gating MOS transistors of each row of the magnetic one-time-programmable memory cells is connected to the word line associated with each row of the magnetic one-time-programmable memory cells.

An integrated circuit constructed on a semiconductor substrate comprising:

• at least one magnetic one-time-programmable memory array comprising:
• a plurality of magnetic one-time-programmable memory cells arranged in rows and columns, wherein each magnetic one-time-programmable memory cell comprises:
• a magnetic tunnel junction (MTJ) device comprising a fixed magnetic layer fabricated on a first electrode, a tunnel barrier insulating layer fabricated upon the fixed magnetic layer, a free magnetic layer fabricated on the tunnel barrier insulating layer, and a second electrode fabricated on the free magnetic layer, wherein a diameter of the MTJ device is chosen such that the tunnel barrier insulating layer is broken down by a program voltage applied across the magnetic one-time-programmable memory cell that approximately equal to is a write voltage for a read/write MRAM memory cell having an equal tunnel barrier insulating layer thickness, and
• a gating metal oxide semiconductor (MOS) transistor serially connected to the MTJ device,
• a plurality of pairs of bit lines wherein a first bit line of the pairs of bit lines is connected to the second electrode of the MTJ device of the magnetic one-time-programmable memory cells of an associated column of the array, a second bit line of the pairs of bit lines is connected to the source of the gating MOS transistor of the magnetic one-time-programmable memory cells of the associated column of the array, and
• a plurality of word lines wherein each word line is associated with each row of the plurality of magnetic one-time-programmable memory cells such that the gates of gating MOS transistor of each row of the magnetic one-time-programmable memory cells is connected to the word line associated with each row of the magnetic one-time-programmable memory cells;
• and
• at least one magnetic random access memory (MRAM) array configured for having performance and density criteria that match MOS transistor based memory wherein MOS based transistor memory is a static random access memory (SRAM), a dynamic random access memory (DRAM), or flash memory.

A method for forming an integrated circuit constructed on a semiconductor substrate, comprising the steps of:

• forming at least one magnetic one-time-programmable memory array is fabricated on the substrate by the steps of:
• forming multiple magnetic one-time-programmable memory cells by the steps of:
• forming a first magnetic tunnel junction (MTJ) device on the substrate by the steps of:
• fabricating a fixed magnetic layer on a first electrode,
• fabricating a tunnel barrier insulating layer upon the fixed magnetic layer,
• fabricating a free magnetic layer on the tunnel barrier insulating layer, and
• fabricating a second electrode on the free magnetic layer, wherein a diameter of the first MTJ device is chosen such that the tunnel barrier insulating layer is broken down by a program voltage applied across the magnetic one-time-programmable memory cell that approximately equal to is a write voltage for a read/write MRAM memory cell having an equal tunnel barrier insulating layer thickness, and
• forming a gating metal oxide semiconductor (MOS) transistor on the substrate,
• serially connecting the gating MOS transistor to the MTJ device,
• arranging magnetic one-time-programmable memory cells in rows and columns,
• forming a plurality of pairs of bit lines,
• connecting a first bit line of one pair of bit lines to the second electrode of the first MTJ device of the magnetic one-time-programmable memory cells of an associated column of the array, and
• connecting a second bit line of the one pair bit lines is connected to the source of the gating MOS transistor of the magnetic one-time-programmable memory cells of the associated column of the array.

A magnetic one-time-programmable memory cell comprising:

• a magnetic tunnel junction (MTJ) device comprising:
• a free magnetic layer,
• a fixed magnetic layer
• a tunnel barrier insulating layer formed between the free magnetic layer and the tunnel barrier insulating layer, and
• a pair of electrodes fabricated such that one electrode of the pair of electrodes is connected to the free magnetic layer and a second electrode is connected to the fixed magnetic layer,
• wherein a diameter of the MTJ device is chosen such that the tunnel barrier insulating layer is broken down by a program voltage applied across the magnetic one-time-programmable memory cell that approximately equal to is a write voltage for a read/write MRAM memory cell having an equal tunnel barrier insulating layer thickness;
• and
• a gating metal oxide semiconductor (MOS) transistor serially connected to the MTJ device.

A magnetic one-time-programmable memory array comprising:

• a plurality of magnetic one-time-programmable memory cells arranged in rows and columns, each magnetic one-time-programmable memory cell comprising;
• a magnetic tunnel junction (MTJ) device comprising:
• a free magnetic layer,
• a fixed magnetic layer
• a tunnel barrier insulating layer formed between the free magnetic layer and the tunnel barrier insulating layer, and
• a pair of electrodes fabricated such that one electrode of the pair of electrodes is connected to the free magnetic layer and a second electrode is connected to the fixed magnetic layer,
• wherein a diameter of the MTJ device is chosen such that the tunnel barrier insulating layer is broken down by a program voltage applied across the magnetic one-time-programmable memory cell that is approximately equal to a write voltage for a read/write MRAM memory cell having an equal tunnel barrier insulating layer thickness;
• and
• a gating metal oxide semiconductor (MOS) transistor serially connected to the MTJ device such that a drain of the MOS transistor is connected to one of the two electrodes of the MTJ device;
• a plurality of pairs of bit lines wherein a first bit line of the pairs of bit lines is connected to another electrode of the two electrodes of the MTJ device of the magnetic one-time-programmable memory cells of an associated column of the array, a second bit line of the pairs of bit lines is connected to the source of the gating MOS transistor of the magnetic one-time-programmable memory cells of the associated column of the array;
• a plurality of word lines wherein each word line is associated with each row of the plurality of magnetic one-time-programmable memory cells such that the gates of gating MOS transistors of each row of the magnetic one-time-programmable memory cells is connected to the word line associated with each row of the magnetic one-time-programmable memory cells.

An integrated circuit constructed on a semiconductor substrate comprising:

• at least one magnetic one-time-programmable memory array comprising:
• a plurality of magnetic one-time-programmable memory cells arranged in rows and columns, wherein each magnetic one-time-programmable memory cell comprises:
• a magnetic tunnel junction (MTJ) device comprising:
• a free magnetic layer,
• a fixed magnetic layer
• a tunnel barrier insulating layer formed between the free magnetic layer and the tunnel barrier insulating layer, and
• a pair of electrodes fabricated such that one electrode of the pair of electrodes is connected to the free magnetic layer and a second electrode is connected to the fixed magnetic layer,
• wherein a diameter of the MTJ device is chosen such that the tunnel barrier insulating layer is broken down by a program voltage applied across the magnetic one-time-programmable memory cell that is approximately equal to a write voltage for a read/write MRAM memory cell having an equal tunnel barrier insulating layer thickness;
• and
• a gating metal oxide semiconductor (MOS) transistor serially connected to the MTJ device such that a drain of the MOS transistor is connected to one of the two electrodes of the MTJ device;
• a plurality of pairs of bit lines wherein a first bit line of the pairs of bit lines is connected to another electrode of the two electrodes of the MTJ device of the magnetic one-time-programmable memory cells of an associated column of the array, a second bit line of the pairs of bit lines is connected to the source of the gating MOS transistor of the magnetic one-time-programmable memory cells of the associated column of the array;
• a plurality of word lines wherein each word line is associated with each row of the plurality of magnetic one-time-programmable memory cells such that the gates of gating MOS transistor of each row of the magnetic one-time-programmable memory cells is connected to the word line associated with each row of the magnetic one-time-programmable memory cells;
• and
• at least one magnetic random access memory (MRAM) array configured for having performance and density criteria that match MOS transistor based memory wherein MOS based transistor memory is a static random access memory (SRAM), a dynamic random access memory (DRAM), or flash memory.

A method for forming an integrated circuit constructed on a semiconductor substrate, comprising the steps of:

• forming at least one magnetic one-time-programmable memory array is fabricated on the substrate by the steps of:
• forming multiple magnetic one-time-programmable memory cells by the steps of:
• forming at least one magnetic tunnel junction (MTJ) device on the substrate by the steps of:
• fabricating a free magnetic layer,
• fabricating a fixed magnetic layer,
• fabricating a pair of electrodes, such that one electrode of the pair of electrodes is connected to the free magnetic layer and a second electrode of the pair of electrodes is connected to the fixed magnetic layer,
• wherein a diameter of the first MTJ device is chosen such that the tunnel barrier insulating layer is broken down by a program voltage applied across the magnetic one-time-programmable memory cell that is approximately equal to a write voltage for a read/write MRAM memory cell having an equal tunnel barrier insulating layer thickness, and
• forming a gating metal oxide semiconductor (MOS) transistor on the substrate,
• serially connecting the gating MOS transistor to the MTJ device such that one electrode of the pair of electrodes is connected to a drain of the MOS transistor,
• arranging magnetic one-time-programmable memory cells in rows and columns,
• forming a plurality of pairs of bit lines,
• connecting a first bit line of one pair of bit lines to another electrode of the pair of electrode of the first MTJ device of the magnetic one-time-programmable memory cells of an associated column of the array, and
• connecting a second bit line of the one pair bit lines is connected to the source of the gating MOS transistor of the magnetic one-time-programmable memory cells of the associated column of the array.