Reduction of power consumption in flash memory
AssigneeEmpire Technology Development LLC
InventorTong Zhang
Life of this patent
Estimating the term…
Abstract
Technologies are generally described for systems, devices and methods effective to reduce power consumption in flash memory. In some examples, a bit error rate estimator module may estimate two or more bit error rates. The two or more bit error rates may be associated with application of respective voltages to read from a memory. A voltage setup module may be configured to be in communication with the bit error rate estimator module. The voltage setup module may be configured to select a voltage to read from the memory. The voltage may be selected based on the two or more bit error rates and based on an error correction level. The error correction level may be a tolerance level available to correct read errors from the memory.
Claims14
A memory controller, comprising:
- a bit error rate estimator module configured to estimate two or more bit error rates, wherein the two or more bit error rates are associated with application of respective voltages to read from a memory, and
- wherein the two or more bit error rates relate to:
- detection of data from a location in the memory;
- and
- transmission of the data from the location in the memory to the memory controller;
- and
- a voltage setup module configured to be in communication with the bit error rate estimator module, wherein the voltage setup module is further configured to select a voltage to read from the memory based on the two or more bit error rates and based on an error correction level, wherein the selection of the voltage includes a selection of a lowest respective voltage with an associated bit error rate that is less than the error correction level, and
- wherein the error correction level is a tolerance level for correction of read errors from the memory.
A method to operate a memory, the method comprising:
- estimating two or more bit error rates, wherein the estimated two or more bit error rates are associated with application of respective voltages to read from the memory;
- identifying an error correction level for correction of read errors from the memory;
- and
- selecting a voltage to read from the memory based on the estimated two or more bit error rates and the identified error correction level,
- wherein selecting the voltage to read from the memory includes selecting a lowest respective voltage with an associated bit error rate that is less than the identified error correction level.
A non-transitory computer readable storage medium, that includes one or more controller-executable instructions stored thereon which, in response to execution by a controller, adapt the controller to perform or cause to be performed:
- estimation of two or more bit error rates, wherein the two or more bit error rates are associated with application of respective voltages to read from a memory;
- identification of an error correction level for correction of read errors from the memory;
- and
- selection of a voltage to read from the memory based on the estimated two or more bit error rates and the identified error correction level,
- wherein the selection of the voltage to read from the memory includes the selection of a lowest respective voltage with an associated bit error rate that is less than the identified error correction level.
Dependencies are inferred from the claim text.