Semiconductor memory device
OwnerHiroaki Nakano, Mami Kakoi +3inventors
InventorsHiroaki Nakano, Mami Kakoi, Shigeki Nagasaka, Toshiyuki Kouchi, Itaru Yamaguchi
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Abstract
According to one embodiment, a semiconductor memory device includes a plurality of stacked first chips and a second chip. The second chip outputs a first signal to the first chips. The first chip outputs status information at timing based on the received first signal. The first chip shifts the received first signal and outputs the shifted first signal to the first chip of a next stage in synchronization with the first clock signal. The second chip receives a plurality of status information output in a serial manner from the first chips.
Claims18
A semiconductor memory device comprising:
- a plurality of first chips, each of the plurality of first chips including a memory cell array, the first chips being stacked in a multi-stage;
- and
- a second chip, the second chip including a first circuit that outputs, when a first command is received from a controller, a first signal to one of the plurality of first chips, the first command being a command for acquiring status information from the plurality of first chips, the plurality of first chins and the second chin being stacked, wherein
- each of the plurality of first chips includes:
- a third circuit that shifts, in synchronization with a first clock signal, the first signal received from the second chip or the first chip of a previous stage and outputs the shifted first signal to the first chip of a next stage, and
- a second circuit that outputs the status information at a timing based on the first signal received from the second chip or the shifted first signal received from the first chip of the previous stage, the status information including pass/fail information of a program process and an erase process to the memory cell array, ready/busy information, or record protect information;
- and
- the second chip includes a fourth circuit that receives, in a serial manner, a plurality of status information outputted from the plurality of first chips, in synchronization with the first clock signal.
A semiconductor memory device comprising a plurality of first chips, each of the plurality of first chips including a memory cell array,
- wherein the first chip includes
- a second circuit that shifts, in synchronization with a first clock signal, a first signal received from the first chip of the previous stage and outputs the shifted first signal to the first chip of a next stage
- a first circuit that outputs status information at a timing based on the shifted first signal received from the first chip of the previous stage, the status information including pass/fail information of a program process and an erase process to the memory cell array, ready/busy information, or record protect information.
A semiconductor memory device comprising:
- a first chip, a second chip, and a third chip, the second chip including a first memory cell array, the third chip including a second memory cell array, the first, second, and third chips being stacked;
- wherein
- the first chip includes a first circuit that outputs, when a first command is received from a controller, a first signal to the second chip;
- the second chip includes:
- a second circuit that shifts, in synchronization with a first clock signal, the first signal received from the first chip and outputs the shifted first signal to the third chip, and
- a third circuit that outputs first status information at timing based on the first signal received from the first chip;
- the third chip includes:
- a fourth circuit that shifts, in synchronization with the first clock signal, the shifted first signal received from the second chip, and
- a fifth circuit that outputs second status information at timing based on the shifted first signal received from the second chip;
- and
- the first chip further includes:
- a sixth circuit that receives, in a serial manner, the first status information outputted from the second chip and the second status information outputted from the third chip.
Dependencies are inferred from the claim text.