Memory device with progressive row reading and related reading method
AssigneeSTMicroelectronics S.r.l.
InventorsGiovanni Campardo, Salvatore Polizzi
Life of this patent
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Abstract
A memory device includes a memory array with memory cells arranged in rows and columns and with word lines and bit lines. A dummy structure includes a dummy row of dummy cells and a dummy word line. A first pre-charging stage biases a word line of the memory array. An output stage includes a plurality of sense amplifiers. Each sense amplifier generates a corresponding output signal representing a datum stored in a corresponding memory cell pre-charged by the first pre-charging stage. A second pre-charging stage biases the dummy word line simultaneously with the word line biased by the first pre-charging stage. The output stage includes an enable stage, which detects a state of complete pre-charging of an intermediate dummy cell.
Claims20
A memory device comprising:
- a memory array that includes a plurality of memory cells arranged in rows and columns and a plurality of word lines and bit lines;
- a dummy structure comprising a dummy row of dummy cells and a dummy word line;
- a first pre-charging stage configured to bias, in a step of pre-charging of a read operation of the memory array, a word line of the memory array;
- an output stage comprising a plurality of sense amplifiers, each sense amplifier being couplable in an electrically controlled way to a corresponding bit line during the reading operation and configured to generate a corresponding output signal representing a data item stored in a corresponding memory cell coupled to the corresponding bit line and pre-charged by the first pre-charging stage;
- and
- a second pre-charging stage configured to bias the dummy word line simultaneously with the word line biased by the first pre-charging stage;
- and
- wherein the output stage further comprises a first sense-enable stage, which is configured to detect a state of complete pre-charging of a dummy cell intermediate between a first dummy cell and a last dummy cell of the dummy row;
- and
- wherein a first part of the sense amplifiers is configured to generate the corresponding output signals following upon sensing of the state of complete pre-charging of the intermediate dummy cell.
A method for reading a memory device
- wherein the memory device comprises:
- a memory array including a plurality of memory cells arranged in rows and columns and a plurality of word lines and bit lines;
- a dummy structure comprising a dummy row of dummy cells and a dummy word line;
- a pre-charging stage configured to bias, in a step of pre-charging of a read operation of the memory array, a word line of the memory array;
- and
- an output stage comprising a plurality of sense amplifiers, each sense amplifier being couplable in an electrically controlled way to a corresponding bit line during the reading operation and configured to generate a corresponding output signal representing a data item stored in a corresponding memory cell coupled to the corresponding bit line and pre-charged by the pre-charging stage;
- and
- wherein the method comprises:
- biasing the dummy word line simultaneously with the word line biased by the pre-charging stage;
- detecting a state of complete pre-charging of a dummy cell intermediate between a first dummy cell and a last dummy cell of the dummy row;
- and
- by a first part of the sense amplifiers, generating corresponding output signals following upon sensing of the state of complete pre-charging of the intermediate dummy cell.
A memory device comprising:
- a memory array including an array of memory cells arranged in rows and columns, a plurality of word lines and a plurality of bit lines;
- a dummy structure comprising a dummy row of dummy cells and a dummy word line;
- a pre-charge circuit configured to pre-charge of a word line of the memory array and the dummy word line;
- a detection circuit configured to detect a state of complete pre-charging of an intermediate dummy cell between a first dummy cell and a last dummy cell of the dummy row;
- and
- an output stage comprising a plurality of sense amplifiers, each sense amplifier configured to generate a corresponding output signal representing a data item stored in a corresponding memory cell coupled to a corresponding bit line and pre-charged by the pre-charge circuit, wherein a first part of the sense amplifiers are configured to generate corresponding output signals following upon sensing of the state of complete pre-charging of the intermediate dummy cell.
Dependencies are inferred from the claim text.