Three-dimensional memory device with charge carrier injection wells for vertical channels and method of making and using thereof

A three-dimensional memory device comprising:

• an alternating stack of insulating layers and electrically conductive layers and located over a substrate;
• memory stack structures extending through the alternating stack, each of the memory stack structures comprising a memory film and a vertical semiconductor channel;
• a buried source semiconductor layer comprising an n-doped semiconductor material, located between the alternating stack and a first portion of the substrate, and contacting at least one surface of the vertical semiconductor channels;
• p-doped semiconductor material portions embedded within the buried source semiconductor layer and contacting at least one surface of a respective subset of the vertical semiconductor channels, wherein the p-doped semiconductor material portions are laterally spaced from one another by the buried source semiconductor layer;
• and
• a backside trench extending through the alternating stack to a top surface of the buried source semiconductor layer;
• an insulating spacer located at a periphery of the backside trench;
• a backside contact via structure located within the insulating spacer and contacting the buried source semiconductor layer;
• and
• drain regions contacting a top portion of a respective vertical semiconductor channel.

A three-dimensional memory device comprising:

• an alternating stack of insulating layers and electrically conductive layers and located over a substrate;
• memory stack structures extending through the alternating stack, each of the memory stack structures comprising a memory film and a vertical semiconductor channel;
• a buried source semiconductor layer comprising an n-doped semiconductor material, located between the alternating stack and a first portion of the substrate, and contacting at least one surface of the vertical semiconductor channels;
• up-doped semiconductor material portions embedded within the buried source semiconductor layer and contacting at least one surface of a respective subset of the vertical semiconductor channels, wherein the p-doped semiconductor material portions are laterally spaced from one another by the buried source semiconductor layer;
• wherein:
• the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;
• the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
• the substrate comprises a silicon substrate;
• the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
• at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
• the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;
• the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level;
• and
• the array of monolithic three-dimensional NAND strings comprises:
• a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and
• a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.

A three-dimensional memory device comprising:

• an alternating stack of insulating layers and electrically conductive layers and located over a substrate;
• memory stack structures extending through the alternating stack, each of the memory stack structures comprising a memory film and a vertical semiconductor channel;
• a buried source semiconductor layer comprising an n-doped semiconductor material, located between the alternating stack and a first portion of the substrate, and contacting at least one surface of the vertical semiconductor channels;
• and
• p-doped semiconductor material portions embedded within the buried source semiconductor layer and contacting at least one surface of a respective subset of the vertical semiconductor channels, wherein the p-doped semiconductor material portions are laterally spaced from one another by the buried source semiconductor layer,
• wherein each of the p-doped semiconductor material portions contacts multiple vertical semiconductor channels.