Semiconductor memory device and data erasing method

A semiconductor memory device comprising:

• a memory cell array including a first memory string and a second memory string, the first memory string including memory cells that are disposed in a first layer, the second memory string including memory cells that are disposed in a second layer above the first layer;
• and
• a controller configured to perform an erasing operation on the memory cells, the erasing operation including a first period during which an erasing pulse is applied to the memory cells of the second memory string, and the erasing pulse is not applied to the memory cells of the first memory string, and a second period directly after the first period during which the erasing pulse is applied to both the memory cells of the first memory string and the memory cells of the second memory string.