Memory device, memory module, and memory system
AssigneeSamsung Electronics Co., Ltd.
InventorsJong-Pil Son, Uk-Song Kang
Life of this patent
Estimating the term…
Abstract
A memory device includes a memory cell array, a data pattern providing unit, and a write circuit. The memory cell array includes a plurality of memory regions. The data pattern providing unit is configured to provide a predefined data pattern. The write circuit is configured to, when a first write command and an address signal are received from an external device, write the predefined data pattern provided from the data pattern providing unit to a memory region corresponding to the address signal.
Claims18
A memory device comprising:
- a memory cell array comprising a plurality of memory regions;
- a data pattern providing unit configured to provide a predefined data pattern;
- a write circuit configured to, when a first write command and an address signal are received from an external device, write the predefined data pattern provided from the data pattern providing unit to a memory region corresponding to the address signal;
- and
- a data input buffer configured to receive data from the external device,
- wherein the data input buffer receives the data from the external device when a second write command is received from the external device and does not receive the data from the external device when the first write command is received from the external device.
A memory system comprising:
- a memory controller configured to receive input data to be written and a write request from an external source, to compare the input data to a predefined data pattern, and when the input data matches the predefined data pattern, to transmit a pattern write command and address information;
- and
- a memory device configured to internally output the predefined data pattern in response to the pattern write command and write the predefined data pattern to a memory region corresponding to the address information.
A method of writing data in a memory system comprising a memory device and a memory controller, the method comprising:
- defining a predefined data pattern;
- receiving a pattern write command and a first address signal from the memory controller;
- generating the predefined data pattern in response to the pattern write command;
- writing the predefined data pattern to a memory region corresponding to the first address signal,
- receiving a data read request from a host;
- transmitting a read command and a second address signal to the memory device;
- reading data from a memory region corresponding to the second address signal;
- determining whether the data matches the predefined data pattern;
- transmitting a matching signal and pattern information to the memory controller when the data matches the predefined data pattern;
- and
- transmitting the data to the memory controller when the data does not match the predefined data pattern.
Dependencies are inferred from the claim text.