Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device, comprising

• a memory cell array configured as an arrangement of NAND cell units each including a memory string and select transistors connected to both ends of the memory string respectively, the memory string including a plurality of nonvolatile memory cells connected in series, the nonvolatile memory cells including dummy cells which are not used for data storage provided at the both ends of the memory string and memory cells for data storage which are capable of storing multi-bit data provided between the dummy cells in the memory string;
• word lines connected to control gate electrodes of the memory cells for data storage;
• dummy word lines connected to control gate electrodes of the dummy cells;
• bit lines connected to first ends of the NAND cell units;
• a source line connected to second ends of the NAND cell units;
• and
• a control circuit configured to perform an erasing operation by applying an erasing voltage to the NAND cell units arranged in a block, the NAND cell units that share the word lines forming the block,
• before the erasing operation for the NAND cell units, the control circuit being configured to execute a pre-program operation in which a certain pre-program voltage is applied to the memory cells for data storage in the NAND cell units and a voltage different from the certain pre-program voltage is applied to the dummy cells in the NAND cell units, and after the pre-program operation is finished, the control circuit being configured to start the erasing operation without performing a verify operation, and
• after the erasing operation for the NAND cell units, the control circuit being configured to execute an erasing verify operation to check whether the memory cells for data storage in the NAND cell units are in an erased state or not in which a certain voltage is applied to the word lines as well that are connected to the control gate electrodes of the memory cells for data storage to be checked in the erased state or not in the NAND cell units.