Semiconductor memory device
AssigneeToshiba Memory Corporation
InventorKoji Hosono
Life of this patent
Estimating the term…
Abstract
According to one embodiment, a semiconductor memory device includes memory units each includes a first transistor, memory cell transistors, and a second transistor serially coupled between first and second ends. A memory cell transistor of each memory unit has its gate electrode coupled to each other. A bit line is coupled to the first ends. First and second drivers output voltage applied to selected and unselected first transistors, respectively. Third and fourth drivers output voltage applied to selected and unselected second transistors, respectively. A selector couples the gate electrode of the first transistor of each memory unit to the first or second driver, and that of the second transistor of each memory unit to the third or fourth driver.
Claims15
A semiconductor memory device comprising:
- more than three first memory units each comprising a first select gate transistor;
- a second select gate transistor;
- and memory cell transistors serially coupled in series between the first select gate transistor and the second select gate transistor;
- a plurality of first lines coupled to the first select gate transistors such that one respective first line is connected to one respective first select gate transistor;
- a plurality of second lines coupled to the second select gate transistors such that one respective second line is connected to one respective second select gate transistor;
- a plurality of third lines coupled to the memory cell transistors such that one respective third line is connected to one respective memory cell transistor;
- a plurality of drivers including (i) only two first drivers configured to be connected to the first select gate transistors and only two second drivers configured to be connected to the second select gate transistors, the only two first drivers including (ia) a first drain select driver that outputs only a selecting voltage that selects the first select gate transistors and (ib) a first drain unselect driver that outputs only an unselecting voltage that unselects the first select gate transistors, and the plurality of drivers further including (ii) drivers for the memory cell transistors;
- and
- a plurality of first drive transistors coupled to the first lines and a second common signal line such that one respective first drive transistor is coupled to either one respective first line or one respective second line, gates of the first drive transistors connected to a third common signal line.
A semiconductor memory device comprising:
- more than three first memory units each comprising a first select gate transistor and a plurality of memory cells electrically coupled in series;
- a plurality of first lines coupled to the first select gate transistors such that one respective first line is connected to one respective first select gate transistor;
- a plurality of first drivers for the first select gate transistors, a number of the first drivers for the first select gate transistors being less than a number of the first lines, the plurality of first drivers including (ia) a first drain select driver that outputs only a selecting voltage that selects the first select gate transistors and (ib) a first drain unselect driver that outputs only an unselecting voltage that unselects the first select gate transistors, one of the first drivers for the first selection transistors being configured to couple to one of the first lines;
- and
- a plurality of first drive transistors coupled to the first lines and a second common signal line such that one respective first drive transistor is coupled to either one respective first line or one respective second line, gates of the first drive transistors connected to a third common signal line.
Dependencies are inferred from the claim text.