Enhanced erasing of two-terminal memory
AssigneeCrossbar, Inc.
InventorsZhi Li, Tanmay Kumar, Sung Hyun Jo
Life of this patent
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Abstract
Two-terminal memory can be set to a first state (e.g., conductive state) in response to a program pulse, or set a second state (e.g., resistive state) in response to an erase pulse. These pulses generally provide a voltage difference between the two terminals of the memory cell. Certain electrical characteristics associated with the pulses can be manipulated in order to enhance the efficacy of the pulse. For example, the pulse can be enhanced or improved to reduce power-consumption associated with the pulse, reduce a number of pulses used to successfully set the state of the memory cell, reduce wear or damage to the memory cell, or to improve Ion or Ioff distribution associated with changing the state of the memory cell.
Claims24
A memory device, comprising:
- an array of memory cells comprising a two-terminal memory cell that includes an interface layer situated between a top electrode and a bottom electrode;
- a controller device that asserts an erase pulse that erases the two-terminal memory cell characterized by setting the two-terminal memory cell to a resistive state;
- and
- an optimization component that optimizes the erase pulse, asserted by the controller device, based on a first algorithm that asserts a lower magnitude voltage during a first period of the erase pulse and a higher magnitude voltage during a second period of the erase pulse, wherein the lower magnitude voltage is substantially constant during the first period, wherein the higher magnitude voltage is greater in magnitude than the lower magnitude voltage, and wherein the first period is significantly longer than the second period.
A method, comprising:
- receiving, by a controller of a memory device, an instruction to erase a two-terminal memory cell comprising an interface layer situated between a first terminal and a second terminal, wherein the instruction to erase relates to setting the two-terminal memory cell to a resistive state;
- determining, by the controller, a first set of electrical characteristics to be applied during a first period of an erase pulse that, when applied to the two-terminal memory cell, sets the two-terminal memory cell to the resistive state, wherein the first set of electrical characteristics indicate a first voltage sufficient to facilitate ionization of active metal particles included in the interface layer of the two-terminal memory cell, and wherein the ionization of the active metal particles is in response to joule-heating produced during the first period;
- and
- determining, by the controller, a second set of electrical characteristics that differ from the first set of electrical characteristics and are associated with a second period of the erase pulse, wherein the second set of electrical characteristics indicate a second voltage sufficient to facilitate driving the active metal particles at least in part toward an active metal layer of the two-terminal memory cell, wherein the second voltage is greater than the first voltage and the first period is significantly greater than the second period.
A method, comprising:
- receiving, by a controller of a memory device, an instruction to erase a two-terminal memory cell comprising an interface layer situated between a first terminal and a second terminal, wherein the instruction to erase relates to setting the two-terminal memory cell to a resistive state;
- determining, by the controller, a first set of electrical characteristics to be applied during a first period of an erase pulse, wherein the erase pulse is determined to be suitable to set the two-terminal memory cell to the resistive state, and wherein the first set of electrical characteristics comprises application of a lower magnitude voltage that is substantially constant during the first period;
- determining, by the controller, a second set of electrical characteristics to be applied during a second period of the erase pulse, wherein the second set of electrical characteristics comprises application of a higher magnitude voltage that is greater in magnitude than the lower magnitude voltage;
- and
- asserting, by the controller, the erase pulse having the lower magnitude voltage during the first period and the higher magnitude voltage during the second period, wherein the first period is greater than the second period by at least a factor of about ten.
Dependencies are inferred from the claim text.