US 9,805,792 B2 · Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices

Abstract

Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline.

Claims41

Dependent claims

A memory array comprising:

a plurality of memory devices individually comprising:
first and second nodes;
a memory element configured to have different memory states;
and
circuitry configured to conduct a first current between the first node and the memory element of the individual memory device at one moment in time and configured to conduct a second current between the memory element and the second node of the individual memory device at another moment in time.

2 more elements

Dependencies are inferred from the claim text.

Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices

Life of this patent

Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices

Life of this patent

Abstract

Claims41