Array power supply-based screening of static random access memory cells for bias temperature instability

A method of testing memory cells arranged in rows and columns in a memory array of an integrated circuit, each memory cell comprising first and second cross-coupled inverters and a first pass transistor, each column of memory cells associated with a first bit line coupled to the first pass transistor of each memory cell in the column, each row of memory cells associated with a word line coupled to gates of the pass transistors of the memory cells in the row;

• wherein, in operation, the first and second inverters are each biased from first and second array bias nodes;
• the method comprising:
• writing a first data state to a selected memory cell under normal bias conditions;
• applying a reduced bias at the first array bias node of the first inverter of the selected memory cell relative to a bias applied at the first array bias node of the second inverter of the selected memory cell;
• and
• during the applying step, accessing the selected memory cell.