Calibration circuit and memory device including the same
AssigneeSamsung Electronics Co., Ltd.
InventorKyung-soo Ha
Life of this patent
Estimating the term…
Abstract
A memory device may include a calibration circuit configured to perform a calibration operation of generating a pull-up control code and a pull-down control code in a calibration mode, and in a stress applying mode, turn on at least one of each of first and second transistor units to apply stress, and an on-die termination (ODT)/off-chip driver (OCD) circuit, a resistance value of the ODT/OCD circuit being adjusted in response to at least one of the pull-up control code and the pull-down control code. The calibration circuit includes a pull-up control code generator including the first transistor unit and a pull-down control code generator including the second transistor unit.
Claims19
A memory device comprising:
- a calibration circuit configured to perform a calibration operation of generating a pull-up control code and a pull-down control code in a calibration mode of the memory device, the calibration circuit including a first set of transistors to which the pull-up control code is supplied, a second set of transistors to which the pull-down control code is supplied, and a third set of transistors connected to a first pad;
- an output driver circuit, a resistance value of the output driver circuit being adjusted in response to at least one bit of the pull-up control code and at least one bit of the pull-down control code;
- and
- a mode control circuit configured to generate a stress enable signal for allowing the calibration circuit to enter a first mode of the memory device,
- wherein the calibration circuit is configured such that the pull-up control code has a logic state which activates at least one transistor of the first set of transistors in the calibration mode and in the first mode different from the calibration mode.
A calibration circuit for controlling an output driver circuit of a memory device, the calibration circuit comprising:
- a first set of PMOS transistors configured to be used to generate a pull-up control code that is supplied to the output driver circuit;
- a first code control circuit configured to supply a first internal code to the first set of PMOS transistors in a calibration mode, and to generate the pull-up control code according to a calibration result;
- a first set of NMOS transistors configured to be used to generate a pull-down control code that is supplied to the output driver circuit;
- and
- a second code control circuit configured to supply a second internal code to the first set of NMOS transistors in the calibration mode, and to generate the pull-down control code according to a calibration result,
- wherein the calibration circuit is configured such that the pull-up control code has a logic state which activates at least one PMOS transistor of the first set of PMOS transistors in the calibration mode and in a stress applying mode different from the calibration mode.
A memory device comprising:
- a calibration circuit including a first set of transistors connected to a first power voltage, a second set of transistors connected to the first set of transistors and a second power voltage, and a third set of transistors connected to a first pad, the calibration circuit configured to, when the memory device is in a calibration mode, generate a first pull-up control code supplied to the first set of transistors and to generate a first pull-down control code supplied to the second set of transistors,
- wherein the calibration circuit is configured to:
- in the calibration mode, generate the first pull-up control code having a logic state which activates at least one transistor of the first set of transistors, and
- in a first mode of the memory device different from the calibration mode, generate the first pull-up control code having a logic state which activates at least one transistor of the first set of transistors.
Dependencies are inferred from the claim text.