Apparatuses and methods for a memory device with dual common data I/O lines
AssigneeMicron Technology, Inc.
InventorsShunichi Saito, Toshio Sugano, Atsushi Hiraishi, Atsuo Koshizuka
Life of this patent
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Abstract
Apparatuses are presented for a semiconductor device utilizing dual I/O line pairs. The apparatus includes a first I/O line pair coupled to a first local I/O line pair. A second I/O line pair may be provided coupled to a second local I/O line pair. The apparatus may further include a first bit line including at least a first memory cell and a second memory cell, and a second bit line including at least a third memory cell and a fourth memory cell may be provided. The first local I/O line pair may be coupled to at least one of the first and second bit lines, and the second local I/O line pair is coupled to at least one of the first and second bit lines.
Claims20
An apparatus comprising:
- a first main I/O line pair comprising a first main I/O line and a second main I/O line;
- a second main I/O line pair comprising a third main I/O line and a fourth main I/O line;
- a first local I/O line pair comprising a first local I/O line coupled to the first main I/O line and a second local I/O line coupled to the second main I/O line;
- a second local I/O line pair comprising a third local I/O line coupled to the third main I/O line and a fourth local I/O line coupled to the fourth main I/O line;
- and
- a first bit line communicatively coupled to at least a first memory cell and a second memory cell;
- and
- a second bit line communicatively coupled to at least a third memory cell and a fourth memory cell;
- wherein the first local I/O line pair is coupled to at least one of the first and second bit lines, and
- wherein the second local I/O line pair is coupled to at least one of the first and second bit lines.
An apparatus comprising:
- one or more memory cell arrays comprising a plurality of memory cells, each memory cell array comprising a plurality of word lines and bit lines, wherein each of the word lines and each of the bit lines is coupled to at least one memory cell;
- at least one sense amplifier coupled to the at least one memory cell of each bit line;
- a first common data I/O line pair comprising a first I/O line pair coupled to a first local I/O line pair, wherein the first local I/O line pair is coupled to a first bit line via a first sense amplifier;
- a second common data I/O line pair comprising a second I/O line pair coupled to a second local I/O line pair, wherein the second local I/O line pair is coupled to at least one of the first bit line via the first sense amplifier, or a second bit line via a second sense amplifier.
An apparatus comprising:
- a first bit line including at least a first memory cell and a second memory cell and a first column address;
- and
- a second bit line including at least a third memory cell and a fourth memory cell and a second column address;
- a first sense amplifier coupled to the first bit line and in communication with the first and second memory cells;
- a second sense amplifier coupled to the second bit line and in communication with the third and fourth memory cells;
- a first common data I/O line pair comprising a first I/O line pair coupled to a first local I/O line pair;
- a first transfer gate coupled between the first sense amplifier and the first local I/O line pair and configured to selectively couple the first local I/O line pair to the first sense amplifier;
- a second common data I/O line pair comprising a second I/O line pair coupled to a second local I/O line pair;
- a second transfer gate coupled between the second sense amplifier and the second local I/O line pair and configured to selectively couple the second local I/O line pair to the second sense amplifier;
- at least one first column decoder configured to activate the first transfer gate, based at least in part on the first or second column address.
Dependencies are inferred from the claim text.