Semiconductor device
AssigneeMicron Technology, Inc.
InventorsYutaka Ito, Yuan He
Life of this patent
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Abstract
A semiconductor device according to an aspect of the present invention has: a plurality of memory cells MC; a plurality of word lines WL each coupled to a corresponding one of the plurality of memory cells MC; and a control circuit that intermittently monitors accesses to the plurality of word lines WL, stores/erases some captured row-addresses in a first number of registers, and detects, by comparison with stored addresses, in response to a first number of accesses to one of the word lines WL in a first period of time. According to the present invention, access histories can be precisely analyzed by a small-scale circuit configuration, and measures against, for example, the Row Hammer problem, etc. can be taken.
Claims14
An apparatus comprising:
- a plurality of memory cells;
- a plurality of word lines each coupled to a corresponding one of the plurality of memory cells;
- and
- a control circuit configured to monitor accesses to the plurality of word lines intermittently and further configured to detect if a first number of accesses have been issued to one of the plurality of word lines in a first period of time,
- wherein the control circuit includes a signal generator configured to receive a first control signal activated when the plurality of word lines are accessed and further configured to activate a second control signal when the first control signal is activated by the first number of times.
An apparatus comprising:
- a plurality of word lines having mutually different allocated addresses;
- an address output circuit configured to provide the address;
- a row decoder configured to access any of the plurality of word lines indicated by the address in response to a first control signal;
- a first latch circuit configured to latch the address in response to a second control signal different from the first control signal;
- a first comparator circuit configured to compare the address output from the address output circuit and the address latched by the first latch circuit in response to the second control signal, and
- wherein the second control signal is less frequently activated than the first control signal.
An apparatus comprising:
- a plurality of word lines having mutually different allocated addresses;
- an address output circuit configured to provide the address;
- a row decoder configured to access any of the plurality of word lines indicated by the address in response to a first control signal;
- a first latch circuit configured to latch the address in response to a second control signal different from the first control signal;
- a first comparator circuit configured to compare the address output from the address output circuit and the address latched by the first latch circuit in response to the second control signal;
- and
- an address scrambler configured to generate an additional address related to and different from the address latched by the first latch circuit in response to activation of a third control signal when the address from the address output circuit and the address latched by the first latch circuit match.
An apparatus comprising:
- a plurality of word lines having mutually different allocated addresses;
- an address output circuit configured to provide the address;
- a row decoder configured to access any of the plurality of word lines indicated by the address in response to a first control signal;
- a first latch circuit configured to latch the address in response to a second control signal different from the first control signal;
- a first comparator circuit configured to compare the address output from the address output circuit and the address latched by the first latch circuit in response to the second control signal;
- a second latch circuit configured to latch the address output from the address output circuit in response to activation of the third control signal;
- and
- a second comparator circuit configured to compare the address from the address output circuit and the address latched by the second latch circuit in response to the third control signal.
Dependencies are inferred from the claim text.