Memory device capable of determining candidate wordline for refresh and control method thereof

A memory device, comprising:

• a plurality of normal wordlines;
• a plurality of redundant wordlines;
• an address generation circuit, for generating a first intermediate address according to a row address, wherein the first intermediate address comprises a first wordline address and a first identification code, and the first identification code indicates whether a first wordline indicated by the first wordline address is a normal wordline or a redundant wordline;
• an address processing circuit, coupled to the address generation circuit, the address processing circuit arranged for referring to the first intermediate address to generate a second intermediate address indicating a second wordline adjacent to the first wordline, wherein the second intermediate address comprises a second wordline address and a second identification code, the second wordline address indicates the second wordline, and the second identification code indicates whether the second wordline is a normal wordline or a redundant wordline;
• and
• a refresh control circuit, coupled to the address processing circuit, the refresh control circuit arranged for determining a disturbance count of the second wordline each time the first wordline is activated, and referring to the disturbance count to determine whether to output the second wordline address to refresh the second wordline, wherein the disturbance count indicates a number of times the second wordline is disturbed due to activation of one or more wordlines adjacent to the second wordline.