Semiconductor memory device

A method of controlling a magnetoresistive random access memory, comprising:

• receiving a plurality of first signals associated with an active state through command/address pins at a rising edge and a falling edge of a clock signal;
• receiving a plurality of second signals associated with a column address and a row address for a read operation, after receiving the plurality of first signals, through the command/address pins at a rising edge and a falling edge of the clock signal;
• reading data from at least one memory cell, in response to the plurality of second signals, according to the row address for the read operation;
• receiving a plurality of third signals associated with a column address and a row address for a write operation through the command/address pins at a rising edge and a falling edge of the clock signal, while reading the data from the at least one memory cell;
• outputting the data read from the at least one memory cell to data input/output pins, according to the column address for the read operation, after a lapse of a predetermined read latency from receiving the plurality of second signals;
• inputting data through the data input/output pins, in response to the plurality of third signals, according to the column address for the write operation, after a lapse of a predetermined write latency from receiving the plurality of third signals;
• and
• writing the data inputted from the data input/output pins to at least one memory cell according to the row address for the write operation.