US 9,805,780 B2Granted

Nonvolatile memory with magnetoresistive element and transistor

AssigneeKabushiki Kaisha Toshiba

InventorsShogo Itai, Hiroki Noguchi

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Abstract

A nonvolatile memory of an embodiment includes: first through fifth wirings; and a memory cell including: a first circuit including a first magnetoresistive element and a first select transistor, the first magnetoresistive element and the first select transistor being electrically connected in series, the first magnetoresistive element including a first reference layer, a first storage layer, and a first nonmagnetic layer between the first reference layer and the first storage layer; a second circuit including a second magnetoresistive element and a second select transistor, the second magnetoresistive element and the second select transistor being electrically connected in series, the second magnetoresistive element including a second reference layer, a second storage layer, and a second nonmagnetic layer between the second reference layer and the second storage layer; a third circuit including first and second transistors; and a fourth circuit including third and fourth transistors.

Claims10

Dependent claims

A nonvolatile memory comprising:

first through fifth wirings;
and
a memory cell including:
a first circuit including a first magnetoresistive element and a first select transistor, the first magnetoresistive element and the first select transistor being electrically connected in series, the first magnetoresistive element including a first reference layer, a first storage layer, and a first nonmagnetic layer between the first reference layer and the first storage layer;
a second circuit including a second magnetoresistive element and a second select transistor, the second magnetoresistive element and the second select transistor being electrically connected in series, the second magnetoresistive element including a second reference layer, a second storage layer, and a second nonmagnetic layer between the second reference layer and the second storage layer;
a third circuit including first and second transistors;
and
a fourth circuit including third and fourth transistors, wherein
gates of the first and second select transistors are electrically connected to the first wiring,
one terminal of the first circuit and a gate of one of the third and fourth transistors of the fourth circuit are electrically connected to the second wiring,
one terminal of the second circuit and a gate of one of the first and second transistors of the third circuit are electrically connected to the third wiring,
the other terminal of the first circuit and a gate of the other one of the third and fourth transistors of the fourth circuit are electrically connected to the fourth wiring, and
the other terminal of the second circuit and a gate of the other one of the first and second transistors of the third circuit are electrically connected to the fifth wiring.

10 more elements

A nonvolatile memory comprising:

a plurality of first wirings;
a plurality of second wirings intersecting the first wirings;
a plurality of third wirings intersecting the first wirings;
a plurality of fourth wirings intersecting the first wirings;
a plurality of fifth wirings intersecting the first wirings;
a first circuit including first and second transistors;
a second circuit including third and fourth transistors;
and
a plurality of memory cells, at least one of the memory cells including:
a third circuit including a first magnetoresistive element and a first select transistor, the first magnetoresistive element and the first select transistor being electrically connected in series, the first magnetoresistive element including a first reference layer, a first storage layer, and a first nonmagnetic layer between the first reference layer and the first storage layer;
and
a fourth circuit including a second magnetoresistive element and a second select transistor, the second magnetoresistive element and the second select transistor being electrically connected in series, the second magnetoresistive element including a second reference layer, a second storage layer, and a second nonmagnetic layer between the second reference layer and the second storage layer, wherein
gates of the first and second select transistors are electrically connected to one of the first wirings,
one terminal of the third circuit and a gate of one of the third and fourth transistors of the second circuit are electrically connected to one of the second wirings,
one terminal of the fourth circuit and a gate of one of the first and second transistors of the first circuit are electrically connected to one of the third wirings,
the other terminal of the third circuit and a gate of the other one of the third and fourth transistors of the second circuit are electrically connected to one of the fourth wirings, and
the other terminal of the fourth circuit and a gate of the other one of the first and second transistors of the first circuit are electrically connected to one of the fifth wirings.

14 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/267,715Filed 16 Sep 2016 · continuation
Priority: 24 Sep 2015
Published: US 2017/0103792 A113 Apr 2017
Granted: 31 Oct 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

G11C 11/161
Using elements in which the storage effect is based on magnetic spin effect: details concerning the memory cell structure, e.g. the layers of the…
G11C 11/16
Using magnetic elements: using elements in which the storage effect is based on magnetic spin effect
G11C 11/1655
Address circuits or decoders: bit-line or column circuits
G11C 11/1657
Address circuits or decoders: word-line or row circuits