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US 9,805,779 B2Granted
Writing to multi-port memories
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsCormac Michael O'Connell, Atul Katoch
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Abstract
A circuit includes a first memory cell and a data control circuit configured to provide first data and second data. The first memory cell has a first port and a second port. The first data is written from the first port to the first memory cell. The second data is based on information of the first data. The second port is configured to write the second data to the first memory cell based on a detection of a write disturb caused by the second port to the first port.
Claims20
A circuit comprising:
- a first memory cell having a first port and a second port;
- a data control circuit configured to provide first data to be written from the first port to the first memory cell and to provide second data based on information of the first data,
- wherein,
- the second port is configured to write the second data to the first memory cell based on a detection of a write disturb caused by the second port to the first port, wherein the write disturb detection is based on a state of a write enable signal of the first memory cell.
1 more element
A method comprising:
- performing a first write operation to a first memory cell based on a first port of the first memory cell, the first port corresponding to a first control line and first data;
- and
- performing a second write operation to the first memory cell based on a second port of the first memory cell, the second port corresponding to a second control line and second data generated based on information of the first data, wherein the second write operation is performed based on a write disturb detection based on a state of a write enable signal,
- wherein
- performing the second write operation is based on a time period corresponding to an activation period of the first control line and an activation period of the second control line.
2 more elements
A method comprising:
- write accessing a first memory cell based on first data and a first port of the first memory cell;
- write or read accessing a second memory cell based on a port of the second memory cell;
- determining whether the first port of the first memory cell and the port of the second memory cell are of a same row;
- and
- based on a result of the determining and on a write disturb detection based on a state of a write enable signal,
- generating second data for a second port of the first memory cell based on information of the first data;
- and
- causing the second port of the first memory cell to write the second data to the first memory cell.
5 more elements
Dependencies are inferred from the claim text.