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US 9,805,777 B2Granted
Sense amplifier
AssigneeArm Limited
InventorsBal S. Sandhu, Cezary Pietrzyk, Robert Campbell Aitken, George McNeil Lattimore
Life of this patent
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Abstract
Broadly speaking, embodiments of the present techniques provide an amplification circuit comprising a sense amplifier and at least one Correlated Electron Switch (CES) configured to provide a signal to the sense amplifier. The sense amplifier outputs an amplified version of the input signal depending on the signal provided by the CES element. The signal provided by the CES element depends on the state of the CES material. The CES element provides a stable impedance to the sense amplifier, which may improve the reliability of reading data from the bit line, and reduce the number of errors introduced during the reading.
Claims13
A circuit comprising:
- an amplifier circuit comprising a first input to receive a first input signal, the amplifier being configured to amplify the first input signal;
- and
- an amplifier control circuit comprising at least one Correlated Electron Switch (CES) element, the amplifier control circuit coupled to the amplifier and arranged to provide at least one signal to the amplifier circuit to provide a stable impedance at the first input of the amplifier circuit, wherein the amplifier circuit comprises a second input to receive a second input signal, wherein the amplifier circuit is configured to amplify a difference between the first input signal and the second input signal, and wherein the amplifier control circuit is configured to provide at least one signal to the amplifier circuit to equalize impedances at the first input and the second input of the amplifier circuit;
- and
- a programming circuit coupled to the amplifier control circuit and configured to provide a first programming signal to the first CES element and a second programming signal to the second CES element, to program the first and second CES elements into a high impedance state or a low impedance state, wherein the programming circuit comprises:
- a first programming circuit connected to the first CES element and configured to provide the first programming signal to the first CES element to program the first CES element to a first impedance state;
- and
- a second programming circuit connected to the second CES element and configured to provide a second programming signal to the second CES element to program the second CES element to the first impedance state,
- wherein the first programming circuit comprises:
- a third transistor connected to the first CES element and configured to receive a program enable signal at a gate input, the program enable signal when asserted enables the first programming circuit to provide the first programming signal, wherein the third transistor is configured to achieve a voltage drop across the third transistor such that a voltage across the first CES element is lower than a first trigger voltage, wherein the first trigger voltage is a voltage at which or above which the first CES element switches from one impedance state to a different impedance state;
- and
- a fourth transistor comprising:
- a third input connected to the third transistor;
- a fourth input coupled to a second power source, wherein the second power source is a programmable power source;
- and
- a first gate input coupled to receive an analog voltage, wherein the analog voltage determines the first programming signal, and
- wherein the second programming circuit comprises:
- a fifth transistor connected to the second CES element and configured to receive a program enable signal at a second gate input, the program enable signal when asserted enables the second programming circuit to provide the second programming signal, wherein the fifth transistor is configured to achieve a voltage drop across the fifth transistor such that a voltage across the second CES element is lower than a second trigger voltage, wherein the second trigger voltage comprises a voltage at which or above which a second CES element switches from one impedance state to a different impedance state;
- and
- a sixth transistor comprising:
- a first terminal connected to the fifth transistor;
- a second terminal coupled to the second power source, wherein the second power source comprises a programmable power source;
- and
- a gate terminal coupled to receive the analog voltage, wherein the analog voltage determines the second programming signal.
21 more elements
A circuit comprising:
- an amplifier circuit comprising a first input to receive a first input signal, the amplifier being configured to amplify the at least one input signal;
- and
- an amplifier control circuit comprising at least one Correlated Electron Switch (CES) element, the amplifier control circuit coupled to the amplifier and arranged to provide at least one signal to the amplifier circuit to provide a stable impedance at the first input of the amplifier circuit,
- wherein the amplifier circuit comprises a second input to receive a second input signal,
- wherein the amplifier circuit is configured to amplify a difference between the first input signal and the second input signal,
- wherein the amplifier control circuit is configured to provide at least one signal to the amplifier circuit to equalize the impedances at the first input and the second input of the amplifier circuit, and
- wherein the amplifier control circuit comprises a first CES element and a second CES element, wherein the first CES element is coupled to the first input of the amplifier circuit, and the second CES element is coupled to the second input of the amplifier circuit;
- a first transistor coupled to the first CES element and configured to receive the first input signal;
- and a second transistor coupled to the second CES element and configured to receive the second input signal,
- the circuit further comprising a first enable circuit comprising:
- a third transistor connected between the first transistor and the first CES element;
- an fourth transistor connected between the second transistor and the second CES element;
- and
- an enable input signal coupled to a gate input of the third transistor and a gate input of the eighth transistor, the enable input signal when asserted allows the first CES element to provide the first signal to the first transistor and the second CES element to provide the second signal to the second transistor,
- wherein the seventh transistor, the fourth transistor and the enable input signal are designed to maintain a determined voltage across the first CES element and the second CES element, wherein the determined voltage is lower than a reset voltage of the first CES element and second CES element.
12 more elements
An apparatus comprising:
- a plurality of memory cells;
- a plurality of sense amplifiers, each sense amplifier coupled to at least one memory cell of the plurality of memory cells and configured to receive at least one bit line input corresponding to the at least one memory cell;
- and
- a plurality of Correlated Electron Switch (CES) elements, coupled to the plurality of sense amplifiers, wherein a first CES element of the plurality of CES elements is coupled between a respective sense amplifier and a first power source, wherein the first CES element is programmed to a first impedance state, and wherein the first CES element provides a first signal to the respective amplifier.
1 more element
Dependencies are inferred from the claim text.