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US 9,805,773 B1Granted
Dual-range clock duty cycle corrector
AssigneeIntel Corporation
InventorsDan Shi, Fangxing Wei, Michael J Allen
Life of this patent
Estimating the term…
Abstract
Examples may include techniques for dual-range clock duty cycle tuning of a clock signal used for an input/output data bus. A clock duty cycle of the clock signal is monitored to determine whether the clock duty cycle falls within a threshold of a 50 percent duty cycle. A dual-range tuning is then implemented until the clock duty cycle of the clock signal falls within the threshold.
Claims22
An apparatus comprising:
- a clock duty cycle monitor logic to monitor a clock duty cycle of a clock signal used for an input/output data bus;
- a determination logic to determine whether the clock duty cycle has a duty cycle percentage within a threshold percentage of a target duty cycle percentage;
- and
- a control signal logic to generate multiple control signals responsive to a determination by the determination logic that the duty cycle percentage falls outside the threshold percentage, the multiple control signals to cause a dual-range tuning of the clock duty cycle, the multiple control signals to include a first control signal to cause a first range of the dual-range tuning that includes at least one coarse adjustment to one or more rising edges of the clock signal to coarsely tune the clock duty cycle that causes the duty cycle percentage to shift approximately 3 percent and the multiple control signals to also include a second control signal to cause a second range of the dual-range tuning that includes at least one fine adjustment to one or more falling edges of the clock signal to finely tune the clock duty cycle that causes the duty cycle percentage to shift approximately 0.5 percent.
1 more element
A method comprising:
- monitoring a clock duty cycle of a clock signal used for an input/output data bus;
- determining whether the clock duty cycle has a duty cycle percentage within a threshold percentage of a target duty cycle percentage;
- and
- generating multiple control signals responsive to determining the duty cycle percentage falls outside the threshold percentage to cause a dual-range tuning of the clock duty cycle, the multiple control signals including a first control signal to cause a first range of the dual-range tuning that includes at least one coarse adjustment to one or more rising edges of the clock signal to coarsely tune the clock duty cycle that causes the duty cycle percentage to shift approximately 3 percent and including a second control signal to cause a second range of the dual-range tuning that includes at least one fine adjustment to one or more falling edges of the clock signal to finely tune the clock duty cycle that causes the duty cycle percentage to shift approximately 0.5 percent.
1 more element
Dependencies are inferred from the claim text.