Three-dimensional (3D) non-volatile semiconductor memory device for loading improvement
AssigneeSK hynix Inc.
InventorSung Lae Oh
Life of this patent
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Abstract
A three-dimensional (3D) non-volatile semiconductor memory device is disclosed. The three-dimensional (3D) non-volatile semiconductor memory device includes: a cell region having a plurality of memory cells; a page buffer formed to store data of the cell region in units of a page; a decoder formed below the cell region, configured to provide a word line voltage to word lines of the cell region; a first upper line formed above the cell region, configured to transfer the word line voltage; a lower interconnection structure formed below the cell region, configured to transfer the word line voltage to the decoder; and a first via disposed between the cell region and the page buffer, configured to couple the first upper line to the lower interconnection structure.
Claims13
A non-volatile semiconductor memory device comprising:
- a cell region having a plurality of memory cells;
- a page buffer that stores data by unit page and disposed a side of the cell region;
- a decoder connection region disposed between the cell region and the page buffer;
- a decoder disposed under the cell region and overlapped with the cell region in a vertical direction;
- an upper global word line disposed in the decoder connection region disposed over the decoder connection region;
- a lower interconnection structure disposed under the cell region and the decoder connection region, and coupled to the decoder;
- and
- a first via disposed in the decoder connection region and connecting the upper global word line and the lower interconnection structure,
- wherein a word line voltage is transferred from the upper global word line through the first via, the lower interconnection structure, and the decoder to the cell region.
A non-volatile semiconductor memory device comprising:
- a cell region provided at a first level;
- a decoder provided at a second level lower than the first level and overlapped with the cell region in a vertical direction;
- a decoder connection region provided at a side of the cell region;
- an upper bit line provided at a third level higher than the first level;
- an upper global word line provided at a fourth level higher than the first level in the decoder connection region;
- an under global word line provided at a fifth level lower than the first level and coupled to the decoder;
- an interconnection line provided at a sixth level lower than the first level and coupled to the under global word line;
- and
- a first via coupling the upper global word line to the interconnection line and provided in the decoder connection region.
A non-volatile semiconductor memory device comprising:
- a cell region having a plurality of memory cells;
- a page buffer that stores data by unit page and disposed a side of the cell region;
- a decoder connection region disposed between the cell region and the page buffer;
- a decoder disposed under the cell region and overlapped with the cell region, configured to provide a word line voltage to word lines of the cell region;
- an upper global word line disposed in the decoder connection region, configured to transfer the word line voltage;
- a lower interconnection structure disposed under the cell region and the decoder connection region, configured to transfer the word line voltage to the decoder;
- and
- a first via disposed in the decoder connection region, configured to couple the upper global word line to the lower interconnection structure to transfer the word line voltage.
Dependencies are inferred from the claim text.