Display controller, video signal transmitting method and system thereof for transmitting video signals with multiple data rate and reduced numbers of signals line

An apparatus, comprising:

• a first display controller that receives a video signal and converts a first partial pixel data of the video signal to a first display control signal that includes data displayed in a first portion of a frame, and converts a second partial pixel data of the video signal to a partial video signal according to an internal clock signal, the partial video signal being outputted together with an external clock signal generated by a clock generator of the first display controller;
• and
• a second display controller that receives the partial video signal and the external clock signal, converts the partial video signal to the second partial pixel data, and converts the second partial pixel data to a second display control signal that includes data displayed in a second portion of the frame, the first and the second portions being different portions of the frame,
• wherein the first display control signal and the second display control signal are used to control an LCD panel to display the frame,
• wherein the partial video signal comprises a data enable (DE) signal, a horizontal synchronization signal, a vertical synchronization signal, a red data, a blue data and a green data, and
• wherein the partial video signal is transmitted with a multiple data rate per clock cycle of the external clock signal such that a number of signal lines needed by the partial video signal is reduced.

An apparatus, comprising:

• a display controller comprising:
• a clock generator, for generating an external clock signal;
• a processing circuit, for receiving a video signal, processing a first partial pixel data of the video signal to output a first display control signal, and outputting a second partial pixel data of the video signal;
• and
• an interface circuit, for receiving the second partial pixel data from the processing circuit, and outputting a partial video signal together with the external clock signal according to the second partial pixel data to another display controller to output a second display control signal accordingly,
• wherein the first display control signal comprises data displayed in a first portion of a frame and the second display control signal comprises data displayed in a second portion of the frame, and
• wherein the interface circuit comprises a packing unit that packages the second partial pixel data into the partial video signal.