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US 9,805,684 B2Granted
Display panel including buffer circuit to compensate for RC delay of a clock signal
AssigneeSamsung Display Co., Ltd.
InventorKwang Sae Lee
Life of this patent
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Abstract
A display panel includes a plurality of pixels, a gate driver, a clock pad, and a buffer circuit. The gate driver supplies gate signals to the plurality of pixels. The clock pad receives a clock signal. The buffer circuit is connected between the clock pad and the gate driver. The buffer circuit compensates for an RC delay of the clock signal received through the clock pad, and supplies the clock signal of which the RC delay is compensated to the gate driver.
Claims18
A display panel, comprising:
- a plurality of pixels;
- a gate driver supplying gate signals to the plurality of pixels;
- a start pad receiving a vertical start signal;
- a clock pad receiving a clock signal;
- a buffer circuit connected between the clock pad and the gate driver,
- wherein the buffer circuit compensates for an RC delay of the clock signal received through the clock pad, and supplies the clock signal of which the RC delay is compensated to the gate driver,
- wherein the gate driver is configured to include a plurality of stages which are cascaded one to another,
- wherein the buffer circuit is configured to be connected between the clock pad and a first stage of the plurality of stages, and
- wherein the first stage is configured to be connected directly to a vertical start line which transfers the vertical start signal supplied from the start pad to the gate driver.
6 more elements
A display panel, comprising:
- a plurality of pixels;
- a gate driver supplying gate signals to the plurality of pixels;
- a clock pad receiving a clock signal;
- and
- a buffer circuit connected between the clock pad and the gate driver,
- wherein the buffer circuit receives the clock signal, compensates for an RC delay of the received clock signal, and outputs the compensated clock signal to the gate driver,
- wherein the buffer circuit includes first and second transistors, wherein the first transistor is connected between a first power line and an output node connected to the gate driver, and the first transistor transfers a first voltage of the first power line to the output node when the clock signal is at a logic high level,
- wherein the second transistor is connected between a second power line and the output node, and the second transistor transfers a second voltage of the second power line to the output node when the clock signal is at a logic low level, and
- wherein a voltage of a gate terminal of the second transistor is lower than the second voltage when the second transistor is turned on and the clock signal is at the logic low level.
6 more elements
Dependencies are inferred from the claim text.