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US 9,805,640 B2Granted
Gate drive apparatus and display apparatus
AssigneesShanghai AVIC Optoelectronics Co., Ltd., Tianma Micro-Electronics Co., Ltd.
InventorsHuijun Jin, Zhiqiang Xia
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Abstract
Embodiments of the invention provide a gate drive apparatus and a display apparatus. With the gate drive apparatus, a clock signal is used in place of a forward scan signal and/or a clock signal is used in place of a backward scan signal and/or a reset signal and a first initial trigger signal (or a second initial trigger signal) are used in place of a low level signal and/or the same signal is used as a first initial trigger signal and a second initial trigger signal to thereby reduce the number of transmission lines for signals driving the gate drive apparatus.
Claims18
A gate drive apparatus, comprising N shift register units,
- wherein a forward select signal terminal of the p-th shift register unit receives a signal output by the (p−2)-th shift register unit, wherein p=3,4,...,N, and a backward select signal terminal of the r-th shift register unit receives a signal output by the (r+2)-th shift register unit, and r=1,2,...,N−2;
- a forward select signal terminal of the first shift register unit receives a first initial trigger signal, and a forward select signal terminal of the second shift register unit receives a second initial trigger signal;
- wherein if N represents an even number, a backward select signal terminal of the second last shift register unit receives the first initial trigger signal, a backward select signal terminal of the last shift register unit receives the second initial trigger signal;
- wherein if N represents an odd number, the backward select signal terminal of the last shift register unit receives the first initial trigger signal, the backward select signal terminal of the second last shift register unit receives the second initial trigger signal;
- wherein a clock block signal terminal of the k-th shift register unit receives a mod((k−1)/4)-th clock signal, wherein k=1,2,...,N;
- wherein a signal received by a forward scan signal terminal of each of the shift register units other than the first two shift register units is the same as the signal received by the clock block signal terminal of the prior shift register unit to the shift register unit, wherein a forward scan signal terminal of the first shift register unit receives a second clock signal, a forward scan signal terminal of the second shift register unit receives a third clock signal;
- wherein when the 0th clock signal is at the high level, the second clock signal is at the low level, and when the 0th clock signal is at the low level, the second clock signal is at the high level;
- when the first clock signal is at the high level, the third clock signal is at the low level, and when the first clock signal is at the low level, the third clock signal is at the high level;
- and wherein an overlapping length of time of a period of time in which the n-th clock signal is at the high level, and a period of time in which the (n+1)-th clock signal is at the high level is no less than a first preset length of time, wherein n=0,1,2,3, and n+1>3, the (n+1)-th clock signal is a mod((n+1)/4)-th clock signal;
- wherein in forward scanning, an overlapping length of time of a period of time in which the first initial trigger signal is at the high level and a period of time in which the second clock signal is at the high level is no less than a period of time it takes to charge a gate of a transistor of a drive gate line in the first shift register unit to the voltage at which the transistor can be turned on stably and the overlapping length of time is no more than one cycle of the second clock signal;
- and
- wherein an overlapping length of time of a period of time in which the second initial trigger signal is at the high level and the period of time in which the third clock signal is at the high level is no less than a period of time it takes to charge a gate of a transistor of a drive gate line in the second shift register unit to the voltage at which the transistor can be turned on stably and the overlapping length of time no more than one cycle of the third clock signal.
9 more elements
A display apparatus, comprising a gate drive apparatus, the gate drive apparatus further comprising N shift register units,
- wherein a forward select signal terminal of the p-th shift register unit receives a signal output by the (p−2)-th shift register unit, wherein p=3,4,...,N, and a backward select signal terminal of the r-th shift register unit receives a signal output by the (r+2)-th shift register unit, wherein r=1,2,...,N−2;
- a forward select signal terminal of the first shift register unit receives a first initial trigger signal, and a forward select signal terminal of the second shift register unit receives a second initial trigger signal;
- wherein if N represents an even number, a backward select signal terminal of the second last shift register unit receives the first initial trigger signal, a backward select signal terminal of the last shift register unit receives the second initial trigger signal;
- wherein if N represents an odd number, the backward select signal terminal of the last shift register unit receives the first initial trigger signal, the backward select signal terminal of the second last shift register unit receives the second initial trigger signal;
- wherein a clock block signal terminal of the k-th shift register unit receives a mod((k−1)/4)-th clock signal, wherein k=1,2,... ,N;
- wherein a signal received by a forward scan signal terminal of each of the shift register units other than the first two shift register units is the same as the signal received by the clock block signal terminal of the prior shift register unit to the shift register unit, wherein a forward scan signal terminal of the first shift register unit receives a second clock signal, a forward scan signal terminal of the second shift register unit receives a third clock signal;
- wherein when the 0th clock signal is at the high level, the second clock signal is at the low level, and when the 0th clock signal is at the low level, the second clock signal is at the high level;
- when the first clock signal is at the high level, the third clock signal is at the low level, and when the first clock signal is at the low level, the third clock signal is at the high level;
- and wherein an overlapping length of time of a period of time in which the n-th clock signal is at the high level, and a period of time in which the (n+1)-th clock signal is at the high level by a length of time is no less than a first preset length of time, wherein n=0,1,2,3, and n+1>3, the (n+1)-th clock signal is a mod((n+1)/4)-th clock signal;
- wherein in forward scanning, an overlapping length of time of a period of time in which the first initial trigger signal is at the high level and a the period of time in which the second clock signal is at the high level is no less than a period of time it takes to charge a gate of a transistor of a drive gate line in the first shift register unit to the voltage at which the transistor can be turned on stably and the overlapping length of time is no more than one cycle of the second clock signal, and
- wherein an overlapping length of time of a period of time in which the second initial trigger signal is at the high level and the period of time in which the third clock signal is at the high level is no less than a period of time it takes to charge a gate of a transistor of a drive gate line in the second shift register unit to the voltage at which the transistor can be turned on stably and the overlapping length of time is no more than one cycle of the third clock signal.
8 more elements
Dependencies are inferred from the claim text.