Selective parasitic extraction
AssigneeMentor Graphics Corporation
InventorsDavid J. Gurney, Sandeep Koranne, Mingchao Wang
Life of this patent
Estimating the term…
Loading patent…
AssigneeMentor Graphics Corporation
InventorsDavid J. Gurney, Sandeep Koranne, Mingchao Wang
Estimating the term…
This application discloses a computing system to pre-process a physical or geometric layout of a circuit design to determine various attributes of the nets, such as a location and a total capacitance for each net in the geometric layout. The computing system can order extraction of the nets from the geometric layout of the circuit design with a space filling curve based, at least in part, on the locations of the nets in the geometric layout of the circuit design and any coupling capacitance between the nets in the geometric layout of the circuit design. The computing system can selectively decouple nets with a coupling capacitance based, at least in part, on the total capacitance for the nets associated with the coupling capacitance. The computing system can generate an electrical representation for each of the extracted nets and write them to a netlist for the circuit design.
A method comprising:
A system comprising:
An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:
Dependencies are inferred from the claim text.