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US 9,804,996 B2Granted
Computation memory operations in a logic layer of a stacked memory
AssigneeAdvanced Micro Devices, Inc.
InventorsJames M. O'Connor, Nuwan S. Jayasena, Gabriel H. Loh, Michael Ignatowski, Michael J. Schulte
Life of this patent
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Abstract
Some die-stacked memories will contain a logic layer in addition to one or more layers of DRAM (or other memory technology). This logic layer may be a discrete logic die or logic on a silicon interposer associated with a stack of memory dies. Additional circuitry/functionality is placed on the logic layer to implement functionality to perform various computation operations. This functionality would be desired where performing the operations locally near the memory devices would allow increased performance and/or power efficiency by avoiding transmission of data across the interface to the host processor.
Claims29
A method comprising:
- receiving, by a logic chip, a computation instruction from a processor, wherein the computation instruction includes a memory access instruction and one or more descriptors;
- decoding, by the logic chip, the computation instruction to identify one or more data elements in a memory chip, the decoding being based on the one or more descriptors, the memory chip and logic chip being integrated within a package and the memory chip being a chip that is separate from the logic chip within the package;
- accessing the one or more data elements based on the memory access instruction;
- and
- performing, by the logic chip, one or more computation operations on the one or more data elements by determining, for each of the one or more computation operations, an output value from:
- (i) a first operand identifying a first data element of the one or more data elements stored at a first memory address in the memory chip;
- and (ii) a second operand identifying either the first data element stored at the first memory address or a second data element of the one or more data elements stored at a second memory address in the memory chip, the performing being implemented without transmitting the one or more data elements to the processor;
- identifying, via a memory interface between the memory chip and the logic chip, for each computation operation, whether to store the corresponding output value in one or more memory addresses in the memory chip according to a determined type of computation operation;
- and
- on a condition that the identifying is directed to the memory chip, providing, for each of the one or more computation operations, the output value to the memory chip.
7 more elements
An apparatus, comprising:
- a memory chip;
- and
- a logic chip coupled to the memory chip to form a memory device, the memory chip and logic chip being integrated within a single package and wherein the logic chip is configured to:
- receive a computation instruction from a processor, wherein the computation instruction includes a memory access instruction and one or more descriptors;
- decode the computation instruction to identify one or more data elements in the memory chip, the decoding being based on the one or more descriptors, the memory chip being a chip that is separate from the logic chip;
- access the one or more data elements based on the memory access instruction;
- and
- perform one or more computation operations on the one or more data elements by determining, for each of the one or more computation operations, an output value from:
- (i) a first operand identifying a first data element of the one or more data elements stored at a first memory address in the memory chip;
- and (ii) a second operand identifying either the first data element stored at the first memory address or a second data element of the one or more data elements stored at a second memory address in the memory chip, the performing being implemented without using the processor;
- a memory interface between the memory chip and the logic chip configured to:
- identify, for each computation operation, whether to store the corresponding output value in one or more memory addresses in the memory chip according to a determined type of computation operation;
- and
- on a condition that the identifying is directed to the memory chip, provide, for each of the one or more computation operations, the output value to the memory chip.
11 more elements
A tangible non-transitory computer-readable medium having stored thereon computer-executable instructions, execution of which by a computing device cause the computing device to perform operations comprising:
- receiving, by a logic chip, a computation instruction from a processor, wherein the computation instruction includes a memory access instruction and one or more descriptors;
- decoding, by the logic chip, the computation instruction to identify one or more data elements in a memory chip, the decoding being based on the one or more descriptors, the memory chip and logic chip being integrated within a package and the memory chip being a chip that is separate from the logic chip within the package;
- accessing the one or more data elements based on the memory access instruction;
- performing, by the logic chip, one or more computation operations on the one or more data elements by determining, for each of the one or more computation operations, an output value from:
- (i) a first operand identifying a first data element of the one or more data elements stored at a first memory address in the memory chip;
- and (ii) a second operand identifying either the first data element stored at the first memory address or a second data element of the one or more data elements stored at a second memory address in the memory chip, the performing being implemented transmitting, for each of the one or more computation operations, the output value to the processor, the performing being implemented without transmitting the one or more data elements to the processor;
- identifying, via a memory interface between the memory chip and the logic chip, for each computation operation, whether to store the corresponding output value in one or more memory addresses in the memory chip according to a determined type of computation operation;
- and
- on a condition that the identifying is directed to the memory chip, providing, for each of the one or more computation operations, the output value to the memory chip.
6 more elements
Dependencies are inferred from the claim text.