Memory system facilitating high bandwidth and high capacity memory

A memory device, comprising:

• an array of memory cells for storing data;
• a plurality of data pins for communicating data with a memory controller over one or more data lane of a memory bus;
• a plurality of detection circuits, each detection circuit being coupled to one of the data pins to detect whether the data lane is coupled to one of the lanes of the memory bus;
• a data buffer in communication with the array of memory cells for providing data to and from the array of memory cells;
• a datapath mapping element coupled between the plurality of data pins and the data buffer for transferring data between the data buffer and the data pins coupled to one of the lanes of the memory bus;
• and
• a control circuit coupled to each detection circuit to identify the data pins that are coupled to one of the lanes of the memory bus, and wherein the control circuit is coupled to the datapath mapping element to cause the datapath mapping element to read and write data to the data buffer using a data stream having a bit width that is the same as the number of data pins coupled to one of the lanes of the memory bus.

A method, comprising:

• a memory controller determining, for each of a plurality of memory devices, a number of memory bus lanes coupled to the memory device, wherein each memory bus lane provides a point-to-point connection between the memory controller and exactly one memory device;
• the memory controller determining an addressing scheme as a function of the determined number of memory bus lanes coupled to each memory device;
• and
• the memory controller reading and writing data to and from the plurality of memory devices over the determined number of memory bus lanes and using the determined addressing scheme, wherein the memory controller communicates with each memory device without using a chip select signal.