Hardware-enforced prevention of buffer overflow
AssigneeThe Johns Hopkins University
InventorJames M. Stevens
Life of this patent
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Abstract
An apparatus having processing circuitry configured to execute applications involving access to memory may include a CPU and a cache controller. The CPU may be configured to access cache memory for execution of an application. The cache controller may be configured to provide an interface between the CPU and the cache memory. The cache controller may include a bitmask to enable the cache controller to employ a two-level data structure to identify memory exploits using hardware. The two-level data structure may include a page level protection mechanism, and a sub-page level protection mechanism.
Claims18
An apparatus comprising processing circuitry configured to execute applications involving access to memory, the apparatus comprising:
- a CPU configured to access cache memory comprising a plurality of cache lines for execution of an application;
- and
- a cache controller configured to provide an interface between the CPU and the cache memory, the cache controller comprising a bitmask to enable the cache controller to employ a two-level data structure including a page level protection mechanism and a sub-page level protection mechanism in parallel to identify memory exploits using hardware,
- wherein the page level protection mechanism comprises designating a selected number of bits corresponding to each cache line as a guard line that, if accessed, indicate a protection fault, and
- wherein at least a portion of at least one guard line is used to store metadata.
A method of providing protection for a CPU relative to accessing cache memory comprising a plurality of cache lines for execution of an application, the method comprising:
- providing a bitmask at a cache controller configured to provide an interface between the CPU and the cache memory;
- and
- employing a two-level data structure including a page level protection mechanism and a sub-page level protection mechanism in parallel to identify memory exploits,
- wherein the page level protection mechanism comprises designating a selected number of bits corresponding to each cache line as a guard line that, if accessed, indicate a protection fault, and
- wherein at least a portion of at least one guard line is used to store metadata.
Dependencies are inferred from the claim text.