Regulating memory activation rates
AssigneeHewlett Packard Enterprise Development LP
InventorsMelvin K. Benedict, William James Walker, Andrew C. Walton
Life of this patent
Estimating the term…
Abstract
Activation rates of memory locations associated with memory addresses are monitored. The activation rates of the memory locations associated with the memory addresses are regulated. The regulating of the activation rates of the memory locations associated with the memory addresses includes selectively updating a cache with the memory addresses based on the activation rates.
Claims15
A method comprising:
- periodically refreshing a plurality of memory locations of a dynamic random access memory (DRAM) device to maintain stored charges within the memory locations, the memory locations associated with a plurality of memory addresses;
- monitoring activation rates of the memory locations, each activation rate associated with a row of the memory locations;
- determining whether a monitored activation rate exceeds a threshold sufficient to cause degradation of data stored in adjacent rows to the row with which the monitored activation rate is associated, regardless of the periodic refreshing of the memory locations of the adjacent rows;
- and
- in response to determining that the monitored activation rate exceeds the threshold, caching the memory addresses associated with the memory locations of the row with which the monitored activation rate is associated.
A system comprising:
- a system memory comprising a dynamic random access memory (DRAM) device having a plurality of memory locations, the memory locations associated with a plurality of memory addresses;
- a cache to a target a first set of the memory addresses;
- and
- a controller to:
- periodically refresh the memory locations of the DRAM device to maintain stored charges within the memory locations;
- monitor activation rates of a second larger set of the memory addresses, each activation rate associated with a row of the memory locations;
- determine whether a monitored activation rate exceeds a threshold sufficient to cause degradation of data stored in adjacent rows to the row with which the monitored activation rate is associated, regardless of the periodic refreshing of the memory locations of the adjacent rows;
- and
- in response to determining that the monitored activation rate exceeds the threshold, update a composition of the first set targeted by the cache to include the memory addresses associated with the memory locations of the row with which the monitored activation rate is associated.
An article comprising a non-transitory storage medium to store instructions readable by a processor-based system which when executed by the processor-based system cause the processor-based system to:
- periodically refresh a plurality of memory locations of a dynamic random access memory (DRAM) device to maintain stored charges within the memory locations, the memory locations associated with a plurality of memory addresses;
- monitor activation rates of the memory locations, each activation rate associated with a row of the memory locations;
- determine whether a monitored activation rate exceeds a threshold sufficient to cause degradation of data stored in adjacent rows to the row with which the monitored activation rate is associated, regardless of the periodic refreshing of the memory locations of the adjacent rows;
- and
- in response to determining that the monitored activation rate exceeds the threshold, cache the memory addresses associated with the memory locations of the row with which the monitored activation rate is associated.
Dependencies are inferred from the claim text.