Invalidating a range of two or more translation table entries and instruction therefor
AssigneeInternational Business Machines Corporation
InventorsTimothy J Slegel, Lisa C Heller, Erwin F Pfeffer, Kenneth E Plambeck
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Abstract
An instruction is provided to perform invalidation of an instruction specified range of segment table entries or region table entries. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof.
Claims20
A computer program product for invalidating a plurality of address translation table entries of a translation table in an emulation environment, wherein dynamic address translation of virtual addresses to main storage address is based on translation tables, the computer program product comprising:
- a non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
- executing, by a processor, a machine instruction, the executing comprising:
- based on the instruction, identifying, by the processor, a plurality of translation table entries;
- invalidating, by the processor, the identified plurality of translation table entries;
- and
- clearing a translation table lookaside buffer (TLB) of entries corresponding to the invalidated translation table entries.
A computer system for invalidating a plurality of address translation table entries of a translation table in an emulation environment, wherein dynamic address translation of virtual addresses to main storage address is based on translation tables, the system comprising:
- a main storage;
- and
- a processor in communications with the main storage wherein the computer system is configured to perform a method comprising:
- executing, by the processor, a machine instruction, the executing comprising:
- based on the instruction, identifying, by the processor, a plurality of translation table entries;
- invalidating, by the processor, the identified plurality of translation table entries;
- and
- clearing a translation table lookaside buffer (TLB) of entries corresponding to the invalidated translation table entries.
A computer implemented method for invalidating a range of two or more address translation table entries of a translation table in an emulation environment, wherein dynamic address translation of virtual addresses to main storage address is based on translation tables, the method comprising:
- executing, by the processor, a machine instruction, the executing comprising:
- based on the instruction, identifying, by the processor, a plurality of translation table entries;
- invalidating, by the processor, the identified plurality of translation table entries;
- and
- clearing a translation table lookaside buffer (TLB) of entries corresponding to the invalidated translation table entries.
Dependencies are inferred from the claim text.