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AssigneeAnalog Devices, Inc.
InventorsJohn A. Hayden, Richard F. Grafton, Matthew Puzey, Gordon Cheung, James Frank Galeotos
Estimating the term…
In safety-critical computer systems, fault tolerance is an important design requirement. Data buses for on-chip interconnection in these processor-based systems are exposed to risk arising from faults in the interconnect itself or in any of the connected peripherals. To provide sufficient fault tolerance, a safety node is inserted between an upstream master section and a downstream slave section of an on-chip bus hierarchy or network. The safety node provides a programmable timeout monitor for detecting a timeout condition for a transaction. If timeout has occurred, the safety node transmits a dummy response back to the master, assumes the role of a master, and waits for the slave device to respond. Furthermore, the safety node rejects any subsequent requests by any of the masters on the upstream section by transmitting a dummy response to those subsequent requests, thus enabling these masters to avoid deadlock or stall.
A safety node within an integrated circuit for monitoring and surviving a timeout on an on-chip interconnect data bus within the integrated circuit, the safety node comprising:
A method for monitoring and surviving a timeout on an on-chip interconnect data bus by a safety node within an integrated circuit to provide a fault tolerance number of one, the safety node comprising an upstream part interfacing with an upstream section of a bus network of the on-chip interconnect data bus connected to one or more masters within the integrated circuit and a downstream part interfacing with a downstream section of the bus network of the on-chip interconnect data bus connected to one or more slaves within the integrated circuit, the method comprising:
A safety-critical integrated circuit comprising:
Dependencies are inferred from the claim text.