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US 9,804,931 B2Granted
Memory mirroring utilizing single write operations
AssigneeRambus Inc.
InventorsSteven Woo, David Secker, Ravindranath Kollipara
Life of this patent
Estimating the term…
Abstract
Memory system enabling memory mirroring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses of the channel may have the same trace length to each of the memory modules within a latency group.
Claims21
A system comprising:
- a memory controller configured to transmit memory data to dual-inline memory modules (DIMMs) using two or more communication channels;
- a first communication channel coupled to said memory controller, the first communication channel comprising a first bus;
- a first set of DIMMs coupled to said first bus;
- a second communication channel coupled to said memory controller, wherein the second communication channel comprises second and third buses;
- a second set of DIMMs coupled to said second bus;
- and
- a third set of DIMMs coupled to said third bus,
- wherein said memory controller is configured to enable storage of a primary copy of data within said second set of DIMMs coupled to said second bus and a secondary copy of data within said third set of DIMMs coupled to said third bus by transmitting a single copy of the data over the second communication channel that is delivered to the second set of DIMMs over the second bus and to the third set of DIMMs over the third bus in a single write operation.
5 more elements
A memory system comprising:
- a memory controller;
- a communication channel coupled to said memory controller and comprising a first bus and a second bus, wherein the memory controller is configured to send a data element in a single data signal over the communication channel;
- and
- a plurality of memory devices coupled to said communication channel and divided into one or more latency groups, wherein each latency group comprises a respective number of memory devices, wherein said communication channel is configured to deliver the single data signal sent from said memory controller to a first memory device of said respective number of memory devices in a first of the one or more latency groups over the first bus and a second memory device of said respective number of memory devices in the first of the one or more latency groups over the second bus in a single write operation to enable storage of a primary copy of the data element within the first memory device and a secondary copy of the data element within the second memory device.
1 more element
A method of storing data to memory devices, said method comprising:
- sending, with a memory controller, a single write operation to a first memory device and a second memory device via a communication channel;
- concurrently activating respective chip selects for said first memory device and said second memory device responsive to said single write operation;
- and
- concurrently sending, with said memory controller, a data element to said first memory device via a first bus of said communication channel and said second memory device via a second bus of said communication channel while the respective chip selects are concurrently activated to store a primary copy of said data element in said first memory device and to store a backup copy of said data element in said second memory device.
1 more element
A system comprising:
- a memory controller configured to transmit memory data to dual-inline memory modules (DIMMs) using two or more communication channels;
- a first communication channel coupled to said memory controller, the first communication channel comprising a first bus;
- a first set of DIMMs coupled to said first bus;
- a second communication channel coupled to said memory controller, wherein the second communication channel comprises second and third buses;
- a second set of DIMMs coupled to said second bus;
- and
- a third set of DIMMs coupled to said third bus,
- wherein said memory controller is configured to enable storage of a primary copy of data within said second set of DIMMs coupled to said second bus and a secondary copy of data within said third set of DIMMs coupled to said third bus by transmitting a single copy of the data over the second communication channel that is delivered to the second set of DIMMs over the second bus with a trace length and to the third set of DIMMs over the third bus with a matched trace length to the second bus.
5 more elements
Dependencies are inferred from the claim text.