US 9,804,920 B2 · Rank and page remapping logic in a volatile memory

Abstract

Embodiments of the inventive concept include a plurality of memory ranks, a buffer chip including a rank remap control section configured to remap a rank from among the plurality of memory ranks of the volatile memory module responsive to a failure of the rank, and a dynamic serial presence detect section configured to dynamically update a stated total capacity of the volatile memory module based at least on the remapped rank. In some embodiments, a memory module includes a plurality of memory ranks, an extra rank in addition to the plurality of memory ranks, the extra rank being a spare rank configured to store a new page corresponding to a failed page from among the plurality of ranks, and a buffer chip including a page remap control section configured to remap the failed page from among the plurality of ranks to the new page in the extra rank.

Claims18

Dependent claims

A volatile memory module, comprising:

a plurality of memory ranks;
a rank remap control section configured to remap a rank from among the plurality of memory ranks of the volatile memory module responsive to a failure of the rank;
and
a dynamic serial presence detect section configured to dynamically update a stated total capacity of the volatile memory module based at least on the remapped rank.

1 more element

A volatile memory module, comprising:

a plurality of memory ranks;
an extra rank in addition to the plurality of memory ranks, the extra rank being a spare rank configured to store a new page corresponding to a failed page from among the plurality of ranks;
and
a page remap control section configured to remap the failed page from among the plurality of ranks to the new page in the extra rank;
wherein the page remap control section further includes:
a page remap table including a mapping between the failed page and the new page;
and
a translation logic section configured to map between the failed page and the new page based at least on the page remap table;
a rank remap control section configured to remap a rank from among the plurality of memory ranks of the volatile memory module responsive to a failure of the rank;
and
a dynamic serial presence detect section configured to dynamically update a stated total capacity of the volatile memory module based at least on the remapped rank,
wherein the translation logic section is configured to decode a page address from a memory request, look up the page remap table to obtain a new page address associated with the new page, and to cause the new page address to be used to carry out the memory request.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application

14/720,934Filed 25 May 2015 · us provisional application

Priority

20 Nov 2014

Published

US 2016/0147623 A126 May 2016

Granted

31 Oct 2017

Term ends

Not estimatedThe source records don’t support an estimate.

Classification15 codes

G06F 11/1048
In individual solid state devices: using arrangements adapted for a specific error detection or correction feature
G06F 11/1016
Using codes or arrangements adapted for a specific type of error: error in accessing a memory location, i.e. addressing error
G06F 11/1666
Error detection or correction of the data by redundancy in hardware: where the redundant component is memory or memory area
G06F 12/0292
User address space allocation, e.g. contiguous or non contiguous base addressing: using tables or multilevel address translation means

Rank and page remapping logic in a volatile memory

Life of this patent

Rank and page remapping logic in a volatile memory

Life of this patent

Abstract

Claims18