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US 9,804,914 B2Granted
Semiconductor memory and semiconductor system using the same
AssigneeSK hynix Inc.
InventorMin Jeong Kim
Life of this patent
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Abstract
A semiconductor memory includes a plurality of path circuits for transmitting data inputted from an exterior source or device to a chip. The semiconductor memory is configured to generate a plurality of pre-error detection signals by detecting whether data transmitted between the plurality of path circuits have errors, and selectively output the plurality of pre-error detection signals.
Claims20
A semiconductor memory comprising:
- a plurality of path circuits for transmitting an external data inputted from an exterior source or device to a chip,
- wherein the semiconductor memory is configured to generate a plurality of pre-error detection signals by detecting whether data transmitted between the plurality of path circuits have errors, and selectively output the plurality of pre-error detection signals.
A semiconductor memory comprising:
- a plurality of chips stacked such that signals are transmitted and received through through electrodes,
- wherein any one of the plurality of chips comprises a plurality of path circuits for transmitting external data to the other chips through the through electrodes, and
- wherein the semiconductor memory is configured to generate a plurality of pre-error detection signals by detecting whether data transmitted between the plurality of path circuits have errors, and selectively output the plurality of pre-error detection signals.
A semiconductor memory comprising:
- a physical layer and a through electrode coupled such that external data and a parity bit corresponding to the external data sequentially pass therethrough;
- a first error detection circuit configured to detect a first pre-error detection signal by using the external data and the parity bit;
- a second error detection circuit configured to detect a second pre-error detection signal by using the external data and the parity bit passing through the through electrode and a memory block;
- and
- a multiplexer configured to output an error detection signal by selecting one of the first pre-error detection signal and the second pre-error detection signal according to a control signal.
2 more elements
Dependencies are inferred from the claim text.