Concurrent validation of hardware units
AssigneeApple Inc.
InventorsAmir Nahir, Randal S. Thelen, Yair Dagan, Yuval Gonczarowski
Life of this patent
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Abstract
A method includes holding a definition of multiple software-implemented tests for testing one or more hardware units of an Integrated Circuit (IC), and of invocation conditions that specify whether the tests are permitted to run. The tests are applied to the hardware units at least partially in parallel, using a processor in the IC, by repeatedly tracking respective execution states of the tests and evaluating the invocation conditions, and invoking a test that currently does not run but is permitted to run in accordance with the invocation conditions.
Claims17
An Integrated Circuit (IC), comprising:
- one or more hardware units on a chip;
- and
- at least one processor, on the chip, which is configured to hold a definition of-multiple software-implemented tests for testing the one or more hardware units, and of corresponding invocation conditions that specify whether the corresponding tests are permitted to run, and to apply the tests to the one or more hardware units for execution at least partially in parallel, by repeatedly tracking respective execution states of the tests and evaluating the corresponding invocation conditions of the tests, and invoking a test that currently does not run but is permitted to run in accordance with its corresponding invocation conditions,
- wherein at least one of the invocation conditions indicates that a corresponding test is permitted to run only if a specific interrupt occurred, a specific hardware signal was received, a certain value was written to a given memory location or a certain time-out has expired,
- wherein the at least one processor is configured to learn actual execution durations of one or more of the tests, and to adjust an invocation time of at least one of the tests based on the actual execution durations, so as to diversify a stress pattern applied to the hardware units.
A method, comprising:
- holding in at least one processor on a chip of an Integrated Circuit (IC), a definition of multiple software-implemented tests for testing one or more hardware units on the chip of the Integrated Circuit (IC), and of corresponding invocation conditions that specify whether the corresponding tests are permitted to run;
- and
- applying the tests to the one or more hardware units for execution at least partially in parallel, by the at least one processor in the IC, by repeatedly tracking respective execution states of the tests and evaluating the corresponding invocation conditions of the tests, and invoking a test that currently does not run but is permitted to run in accordance with its corresponding invocation conditions,
- wherein at least one of the invocation conditions indicates that a corresponding test is permitted to run only if a specific interrupt occurred, a specific hardware signal was received, a certain value was written to a given memory location or a certain time-out has expired,
- wherein applying the tests comprises learning actual execution durations of one or more of the tests, and adjusting an invocation time of at least one of the tests based on the actual execution durations, so as to diversify a stress pattern applied to the hardware units.
A tangible non-transitory computer-readable medium in which program instructions are stored, which instructions, when read by one or more processors in an Integrated Circuit (IC) on a chip, cause the one or more processors to hold a definition of multiple software-implemented tests for testing one or more hardware units on the chip of the IC, and of corresponding invocation conditions that specify whether the corresponding tests are permitted to run, and to execute the tests at least partially in parallel, by repeatedly evaluating the corresponding invocation conditions of the tests, and invoking a test that currently does not run but is permitted to run in accordance with its corresponding invocation conditions,
- wherein at least one of the invocation conditions indicates that a corresponding test is permitted to run only if a specific interrupt occurred, a specific hardware signal was received, a certain value was written to a given memory location or a certain time-out has expired,
- wherein executing the tests comprises learning actual execution durations of one or more of the tests, and adjusting an invocation time of at least one of the tests based on the actual execution durations, so as to diversify a stress pattern applied to the hardware units.
Dependencies are inferred from the claim text.