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US 9,804,896 B2Granted
Thread migration across cores of a multi-core processor
AssigneeEmpire Technology Development LLC
InventorSriram Vajapeyam
Life of this patent
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Abstract
Techniques described herein are generally related to thread migration across processing cores of a multi-core processor. Execution of a thread may be migrated from a first processing core to a second processing core. Selective state data required for execution of the thread on the second processing core can be identified and can be dynamically acquired from the first processing core. The acquired state data can be utilized by the thread executed on the second processing core.
Claims32
A method to migrate a thread from a first processing core to a second processing core of a multi-core processor, the method comprising:
- executing the thread on the first processing core of the multi-core processor;
- migrating the execution of the thread from the first processing core to the second processing core of the multi-core processor;
- detecting a read access by the thread that executes on the second processing core, wherein the read access corresponds to first architectural state data, and wherein the first architectural state data relates to the execution of the thread on the second processing core;
- identifying the first architectural state data, in response to the detection of the read access, based on one or more tags associated with second architectural state data, wherein the one or more tags indicate a status of the second architectural state data as the execution of the thread is migrated from the first processing core to the second processing core, wherein the first architectural state data is associated with a first architectural state of the first processing core, and wherein the second architectural state data is associated with a second architectural state of the second processing core;
- and
- acquiring a first portion of the first architectural state data from the first processing core, wherein the acquired first portion of the first architectural state data is utilized by the thread that executes on the second processing core;
- migrating the execution of the thread from the second processing core to a third processing core of the multi-core processor;
- comparing a first value of a first instruction counter of the first architectural state data with a second value of a second instruction counter of the second architectural state data;
- determining, based on the comparison, that the first value is higher than the second value;
- identifying the first processing core in response to the determination that the first value is higher than the second value;
- acquiring, in response to the identification of the first processing core, a second portion of the first architectural state data from the first processing core;
- and
- executing the thread on the third processing core based on the acquired second portion of the first architectural state data.
10 more elements
A system effective to migrate a thread across cores in a multi-core processor, the system comprising:
- a first processing core;
- a second processing core;
- and
- a third processing core;
- the first processing core being configured to augment first architectural state data, associated with a first architectural state of the first processing core, with one or more first tags;
- the second processing core being configured to augment second architectural state data, associated with a second architectural state of a second processing core, with one or more second tags;
- the first processing core being further configured to migrate execution of the thread from the first processing core to the second processing core;
- the second processing core being further configured to:
- detect a read access by the thread that executes on the second processing core, wherein the detection is based on a use of the one or more second tags associated with the second architectural state data, and wherein the read access corresponds to a first portion of the first architectural state data;
- acquire the first portion of the first architectural state data from the first processing core, in response to the detection of the read access, wherein the acquired first portion of the first architectural state data is utilized by the thread that executes on the second processing core;
- set a migration bit of the first architectural state data, in the first processing core, to indicate a migrated status of the first architectural state data, wherein the migrated status of the first architectural state data is indicative of a completed migration of the first architectural state data from the first processing core to the second processing core;
- and
- migrate the execution of the thread from the second processing core to the third processing core;
- the third processing core being configured to:
- compare a first value of a first instruction counter of the first architectural state data with a second value of a second instruction counter of the second architectural state data;
- based on the comparison, determine that the first value is higher than the second value;
- identify the first processing core in response to the determination that the first value is higher than the second value;
- in response to the identification of the first processing core, acquire a second portion of the first architectural state data from the first processing core;
- and
- execute the thread based on the acquired second portion of the first architectural state data.
17 more elements
A method to migrate a thread across cores in a multi-core processor, the method comprising:
- augmenting first state data, associated with a first architectural state of a first processing core of two or more processing cores of the multi-core processor, with one or more first tags;
- augmenting second state data, associated with a second architectural state of a second processing core of the two or more processing cores of the multi-core processor, with one or more second tags;
- migrating execution of a thread from the first processing core to the second processing core;
- detecting a read access by the thread that executes on the second processing core, by using the one or more second tags associated with the second state data, wherein the read access corresponds to a portion of the first state data;
- acquiring the portion of the first state data from the first processing core, in response to the detection of the read access, wherein the acquired portion of the first state data is utilized by the thread that executes on the second processing core;
- updating a status indicator in the first processing core to indicate a migrated status of the first state data, wherein the status indicator corresponds to the acquired portion of the first state data, and wherein the acquired portion of the first state data includes a first portion of the first state data;
- migrating the execution of the thread from the second processing core to a third processing core of the two or more processing cores of the multi-core processor;
- comparing a first value of a first instruction counter of the first state data with a second value of a second instruction counter of the second state data;
- based on the comparison, determining that the first value is a higher value among the first value and the second value;
- identifying the first processing core, in response to the determination that the first value is the higher value among the first value and the second value;
- in response to the identification of the first processing core, acquiring a second portion of the first state data;
- and
- executing the thread on the third processing core using the acquired second portion of the first state data, wherein updating the status indicator comprises setting a migration bit of the acquired first portion of the first state data and the second portion of the first state data by a coherence module of the first processing core.
10 more elements
A multi-core processor, comprising:
- a plurality of processing cores that includes at least a first processing core, a second processing core, and a third processing core, wherein the first processing core comprises:
- at least a first architectural state component configured to store first architectural state data associated with a first architectural state of the first processing core, wherein the first architectural state data comprises first tags indicative of a status of the first architectural state data;
- and
- a first coherence module that is coupled to the first architectural state component, wherein the second processing core comprises:
- at least a second architectural state component configured to store second architectural state data associated with a second architectural state of the second processing core, wherein the second architectural state data comprises second tags indicative of a status of the second architectural state data;
- and
- a second coherence module that is coupled to the at least the second architectural state component, wherein the second coherence module is configured to:
- identify a first portion of the first architectural state data based on the second tags associated with the second architectural state data, wherein the first portion of the first architectural state data relates to an execution of a thread on the second processing core, and wherein the thread is migrated to the second processing core from the first processing core;
- in response to the identification of the first portion of the first architectural state data, acquire the first portion of the first architectural state data from the first processing core for execution of the migrated thread on the second processing core;
- update a status indicator to indicate a migrated status of the first architectural state data, wherein the migrated status of the first architectural state data is indicative of a completed migration of the first architectural state data from the first processing core to the second processing core;
- and
- migrate the execution of the thread from the second processing core to the third processing core,
- wherein the third processing core is configured to:
- compare a first value of a first instruction counter of the first architectural state data with a second value of a second instruction counter of the second architectural state data;
- based on the comparison, determine that the first value is higher than the second value;
- identify the first processing core, in response to the determination that the first value is higher than the second value;
- in response to the identification of the first processing core, acquire a second portion of the first architectural state data from the first processing core;
- and
- execute the thread on the third processing core based on the acquired second portion of the first architectural state data.
16 more elements
Dependencies are inferred from the claim text.