Systems and methods involving control-I/O buffer enable circuits and/or features of saving power in standby mode
AssigneeGSI Technology, Inc.
InventorsYoung-Nam Oh, Soon Kyu Park, Jae Hyeong Kim
Life of this patent
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Abstract
A method of operating a clock frequency detected control I/O buffer enable circuitry and/or features of saving power. In illustrative implementations, the method may be directed to providing low standby power consumption, such as providing low standby power consumption in high-speed synchronous SRAM and RLDRAM devices.
Claims4
A method of operating a clock frequency detected control input and output buffer enable circuit in a semiconductor device, the method comprising the steps of:
- in a power up operation mode:
- performing a first initialization of the semiconductor device using a first power up signal to initialize an internal power supply;
- and
- performing, after ramp up of the internal power supply and in response to a vref signal, a second initialization of the semiconductor device using a second power up signal to initialize internal peripheral components, the first power up signal voltage is equal to the second power up signal voltage, such that the internal power supply is not used.
A method of operating a clock frequency detected control input and output buffer enable circuit in a semiconductor device, the method comprising the steps of:
- in a power up operation mode:
- performing a first initialization of the semiconductor device using a first power up signal to initialize an internal power supply;
- and
- performing, after ramp up of the internal power supply and in response to a vref signal, a second initialization of the semiconductor device using a second power up signal to initialize internal peripheral components
- wherein the step of performing a first initialization of the semiconductor device internal-dc circuit includes switching a first power up signal to a first power up disable state about 1.0 v from a first enable state in response to ramping up a first external power supply without affecting a state of a first output set signal levels;
- and
- wherein the step of performing a second initialization the semiconductor device internal-peripheral circuit includes switching a second power up signal coupled to an internal vref power up circuit to a second power up disable state by ramping up vref pad voltage level around MOS threshold voltage level from a second enable state without affected to states of a first output set signal levels.
Dependencies are inferred from the claim text.