Branching to alternate code based on runahead determination

A method of operating a microprocessor having a runahead mode comprising:

• encountering an instruction within a processing pipeline of the microprocessor;
• executing and generating output of a condition-testing instruction operable to test whether the microprocessor is operating in the runahead mode when the instruction is encountered and whether the instruction uses a poisoned register;
• and
• branching out of a portion of code containing the instruction based on an output of the condition-testing instruction.

A microprocessor having a runahead mode, comprising:

• a memory;
• a processing pipeline configured to retrieve instructions and data from the memory;
• runahead logic operatively coupled with the processing pipeline and operable to cause the microprocessor to enter the runahead mode upon occurrence of a stall condition in the processing pipeline;
• and
• a portion of code contained in the memory and executable by the processing pipeline, wherein the processing pipeline is configured, in response to encountering the portion of code, to determine whether the microprocessor is in the runahead mode and, responsive to an affirmative determination, to branch to and execute a runahead code portion that correlates to the portion of code in lieu of executing the portion of code, the runahead code portion being configured to identify and resolve latency events which may occur when the portion of code is executed outside of runahead.