Apparatus and method for compressing instruction for VLIW processor, and apparatus and method for fetching instruction

An instruction fetching apparatus for a processor, the instruction fetching apparatus comprising:

• an instruction selector configured to select, from an instruction cache, an instruction bundle at an address indicated by a program counter (PC);
• an instruction buffer configured to store the instruction bundle selected by the instruction selector;
• and
• a No-Operation (NOP) bundle controller configured to control, based on an indicator code corresponding to the instruction bundle forwarded from the instruction buffer to an instruction decoder in a current cycle, fetch of another instruction bundle in a subsequent cycle,
• wherein the NOP bundle controller is configured to extract the indicator code based on a value of a stop bit of each instruction included in the instruction bundle forwarded to the instruction decoder in the current cycle, and
• wherein the NOP bundle controller is configured to determine, based on a value of a stop bit of a first instruction included in the instruction bundle in the current cycle, a size of the indicator code to be extracted.

An instruction compression method comprising:

• determining at least one of No-Operation (NOP) instructions included in an instruction bundle to be executed in a very long instruction word (VLIW) processor and a number of NOP instruction bundles following the instruction bundle;
• generating an indicator code that indicates an issue width of the instruction bundle and the number of the NOP instruction bundles following the instruction bundle;
• and
• compressing the instruction bundle by removing the at least one of the NOP instructions from the instruction bundle and the NOP instruction bundles following the instruction bundle,
• wherein the compressing replaces a stop bit of each instruction of the compressed instruction bundle with a corresponding bit value of the indicator code.