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US 9,804,852 B2Granted
Conditional execution support for ISA instructions using prefixes
AssigneeIntel Corporation
InventorsJonathan D. Combs, Jason W. Brandt, Robert Valentine, Kevin B. Smith, Zia Ansari, Maxim Loktyukhin
Life of this patent
Estimating the term…
Abstract
In one embodiment, a processor includes an instruction decoder to receive a first instruction having a prefix and an opcode and to generate, by an instruction decoder of the processor, a second instruction executable based on a condition determined based on the prefix, and an execution unit to conditionally execute the second instruction based on the condition determined based on the prefix.
Claims18
A processor, comprising:
- an instruction decoder to receive a first instruction having a prefix and an opcode and to generate, by the instruction decoder of the processor, a second instruction executable based on a condition determined based on a vector length bit and three other bits of the prefix that are not utilized in a vector instruction;
- and
- an execution unit to conditionally execute the second instruction based on the condition determined based on the prefix.
A method, comprising:
- receiving, at a processor, first instruction having a prefix and an opcode;
- generating, by an instruction decoder of the processor, a second instruction executable based on a condition determined based on a vector length bit and three other bits of the prefix that are not utilized in a vector instruction;
- and
- conditionally executing, by an execution unit of the processor, the second instruction based on the condition determined based on the prefix.
1 more element
A system, comprising:
- an interconnect;
- a processor coupled the interconnect to receive by an instruction decoder of the processor a first instruction having a prefix and an opcode, and to generate, a second instruction executable based on a condition determined based on a vector length bit and three other bits of the prefix that are not utilized in a vector instruction, and to cause an execution unit to conditionally execute the second instruction based on the condition determined based on the prefix;
- and
- a dynamic random access memory (DRAM) coupled to the interconnect.
1 more element
Dependencies are inferred from the claim text.