US 9,804,851 B2Granted

Operand size control

AssigneeArm Limited

InventorsRichard Roy Grisenthwaite, David James Seal, Philippe Jean-Pierre Raphalen, Lee Douglas Smith

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Abstract

A data processing system is provided with processing circuitry as well as a bank of 64-bit registers. An instruction decoder decodes arithmetic instructions and logical instruction specifying arithmetic operations and logical operations to be performed upon operands stored within the 64-bit registers. The instruction decoder is responsive to an operand size field SF within the arithmetic instructions and the logical instructions specifying whether the operands are 64-bit operands or 32-bit operands where all of the operands are 64-bit operands or all of the operands are 32-bit operands. If a switch is made to a lower exception level, then a check is made as to whether or not a register being used was previously subject to a 64-bit write to that register. If such a 64-bit write had previously taken place, then the upper 32-bits are flushed so as to avoid data leakage from the higher exception level.

Claims23

Dependent claims

An apparatus for processing data comprising:

a plurality of 2N-bit registers, each register configured to store only a single operand;
processing circuitry configured to perform data processing operations;
and
instruction decoder circuitry, coupled to said processing circuitry and responsive to a stream of program instructions of only a fixed size of an instruction set, configured to generate control signals for controlling said processing circuitry to perform said data processing operations;
wherein
said instruction decoder circuitry is configured to decode arithmetic instructions and logical instructions of said instruction set respectively specifying arithmetic operations and logical operations to be performed upon operands stored within said plurality of 2N-bit registers;
and
said instruction decoder circuitry is configured to decode an operand size field within said arithmetic instructions and said logical instructions specifying only one of:
(i) said operands are 2N-bit operands each stored within a separate 2N-bit register of said plurality of 2N-bit registers;
and
(ii) said operands are N-bit operands each stored within a separate 2N-bit register of said plurality of 2N-bit registers.

8 more elements

A method of processing data comprising the steps of:

storing data values within a plurality of 2N-bit registers, each register configured to store only a single operand;
performing data processing operations using processing circuitry;
and
decoding a stream of program instructions of only a fixed size of an instruction set to generate control signals for controlling said processing circuitry to perform said data processing operations;
wherein
said decoding step decodes arithmetic instructions and logical instructions of said instruction set respectively specifying arithmetic operations and logical operations to be performed upon operands stored within said plurality of 2N-bit registers;
and
said decoding decodes an operand size field within said arithmetic instructions and said logical instructions specifying only one of:
(i) said operands are 2N-bit operands each stored within a separate 2N-bit register of said plurality of 2N-bit registers;
and
(ii) said operands are N-bit operands each stored within a separate 2N-bit register of said plurality of 2N-bit registers.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/064,257Filed 14 Mar 2011
Priority: GB 1004300.815 Mar 2010
Published: US 2011/0231633 A122 Sep 2011
Granted: 31 Oct 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G06F 9/3016
Instruction analysis, e.g. decoding, instruction word fields: decoding the operand specifier, e.g. specifier format
G06F 9/3001
To perform operations on data operands: arithmetic instructions
G06F 9/30112
Register structure: comprising data of variable length
G06F 9/3861
Concurrent instruction execution, e.g. pipeline or look ahead: recovery, e.g. branch miss-prediction, exception handling