Space reduction in processor stressmark generation

A computer program product for pruning a design space when generating a maximum power stressmark, the computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to:

• perform a multi-stage design space search process, wherein each stage comprises:
• calculating a number of instructions per cycle (IPC) for each instruction sequence in a set of instruction sequences that place a power stress on a system under analysis;
• removing one or more of the instruction sequences having an IPC lower than a threshold from the set to retain a plurality of the instruction sequences having the IPC above the threshold as a plurality of remaining instruction sequences in the set;
• evaluating at least one power metric of the remaining instruction sequences in the set;
• removing one or more of the instruction sequences from the remaining instruction sequences having at least one power metric evaluated outside of one or more ranges from the set to further prune the remaining instruction sequences based on power;
• and
• passing the remaining instruction sequences in the set to a next stage;
• and
• generate a maximum power stressmark based on the evaluating of the at least one power metric from a final stage;
• and
• executing the remaining instruction sequences to stress test a system under analysis during a design and manufacturing process to reduce processor analysis computational burden on the system.