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US 9,804,848 B2Granted
Instruction and logic for processing text strings
AssigneeIntel Corporation
InventorsMichael A. Julier, Jeffrey D. Gray, Srinivas Chennupaty, Sean P. Mirkes, Mark P. Seconi
Life of this patent
Estimating the term…
Abstract
Method, apparatus, and program for performing a string comparison operation. The apparatus includes execution resources to execute a first instruction. In response to the first instruction, the execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.
Claims11
A hand held device comprising:
- a plurality of system components, including:
- a liquid crystal display controller;
- a dynamic random access memory;
- a direct memory access controller;
- a wireless transceiver;
- a network controller;
- a flash memory device;
- a graphics controller;
- a memory controller;
- and
- an audio controller;
- and
- a processor coupled to the plurality of system components, the processor comprising:
- a decoder to decode a compare instruction;
- a plurality of 64-bit single-instruction multiple data (SIMD) integer data registers, including:
- a first and second 64-bit SIMD integer data register to store a first and second 64-bit SIMD integer operand, respectively, each of the first and second 64-bit SIMD integer operands to include a plurality of integer data elements;
- and
- a 64-bit SIMD destination register, into which at least one result of performing the compare instruction is to be stored, wherein the first and second 64-bit SIMD integer data registers and the 64-bit SIMD destination register are to be identified by a first and second SIMD operand field and a SIMD destination field, respectively, of the compare instruction, and wherein the compare instruction includes a field to indicate one of a plurality of data element sizes for the integer data elements of the first and second 64-bit SIMD integer data operands, including an 8-bit data element size, a 16-bit data element size, and a 32-bit data element size;
- and
- a plurality of execution units, wherein an execution unit of the plurality of execution units is to execute the compare instruction, wherein the compare instruction is to cause the processor to:
- compare integer data elements of the first 64-bit SIMD integer operand with integer data elements of the second 64-bit SIMD integer operand, wherein the integer data elements of the first 64-bit SIMD integer operand to be compared with the integer data elements of the second 64-bit SIMD integer operand are to be in same data element positions, and
- store a plurality of indicators of whether the compared integer data elements of the first 64-bit SIMD integer operand and the integer data elements of the second 64-bit SIMD integer operand are equal, wherein the plurality of indicators are to be expanded data elements, each of a first multi-bit size.
19 more elements
A hand held device comprising:
- a plurality of system components, including:
- a liquid crystal display controller;
- a dynamic random access memory;
- a direct memory access controller;
- a wireless transceiver;
- a network controller;
- a flash memory device;
- a graphics controller;
- a memory controller;
- and
- an audio controller;
- and
- a processor coupled to the plurality of system components, wherein the processor is a RISC processor, the processor comprising:
- a decoder to decode a compare instruction;
- a plurality of 64-bit single-instruction multiple data (SIMD) integer data registers, including:
- a first and second 64-bit SIMD integer data register to store a first and second 64-bit SIMD integer operand, respectively, each of the first and second 64-bit SIMD integer operands to include a plurality of integer data elements;
- and
- a 64-bit SIMD destination register, into which at least one result of performing the compare instruction is to be stored, wherein the first and second 64-bit SIMD integer data registers and the 64-bit SIMD destination register are to be identified by a first and second SIMD operand field and a SIMD destination field, respectively, of the compare instruction, and wherein the compare instruction includes a 2-bit field to indicate one of a plurality of data element sizes for the integer data elements of the first and second 64-bit SIMD integer operands, including an 8-bit data element size, a 16-bit data element size, and a 32-bit data element size;
- and
- a plurality of execution units, wherein an execution unit of the plurality of execution units is to execute the compare instruction, wherein the compare instruction is to cause the processor to:
- compare integer data elements of the first 64-bit SIMD integer operand with integer data elements of the second 64-bit SIMD integer operand, wherein the integer data elements of the first 64-bit SIMD integer operand to be compared with the integer data elements of the second 64-bit SIMD integer operand are to be in same data element positions, and
- store a plurality of indicators of whether the compared integer data elements of the first 64-bit SIMD integer operand and the integer data elements of the second 64-bit SIMD integer operand are equal, wherein the plurality of indicators are to be expanded data elements, each of a first multi-bit size,
- wherein the graphics controller and the memory controller are integrated on a same die as the processor.
20 more elements
Dependencies are inferred from the claim text.