US 9,804,847 B2Granted

Thread context preservation in a multithreading computer system

AssigneeInternational Business Machines Corporation

InventorsJonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner, Lisa Cranton Heller, Jeffrey P. Kubala, Damian L. Osisek, Donald W. Schmidt, Timothy J. Slegel

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Abstract

According to one aspect, a computer-implemented method for thread context preservation in a configuration including a core configurable between a single thread (ST) mode and a multithreading (MT) mode is provided. The ST mode addresses a primary thread, and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. Based on determining, by the core in the MT mode, that MT is to be disabled, switching from the MT mode to the ST mode is performed, where the primary thread of the MT mode is maintained as the primary thread of the ST mode. A thread context including program accessible register values and program counter values of the one or more secondary threads is made inaccessible to programs. Based on the switching, any one of clearing the program accessible register values or retaining the program accessible register values is performed.

Claims8

Dependent claims

A computer implemented method for thread context preservation in a configuration comprising a core configurable between a single thread (ST) mode and a multithreading (MT) mode, the ST mode addressing a primary thread and the MT mode addressing the primary thread and one or more secondary threads on shared resources of the core, the method comprising:

based on determining, by the core in the MT mode, that MT is to be disabled in response to a reset or a deactivation, switching from the MT mode to the ST mode, wherein the primary thread of the MT mode is maintained as the primary thread of the ST mode, wherein a thread context comprising program accessible register values and program counter values of the one or more secondary threads is made inaccessible to programs by shifting an expanded address value comprising a core address value and a thread address value to eliminate the thread address value based on a requested maximum thread identifier;
and
based on the switching, performing any one of clearing the program accessible register values or retaining the program accessible register values.

Dependencies are inferred from the claim text.

Facts

Application: 14/819,592Filed 6 Aug 2015 · continuation
Priority: 27 Mar 2014
Published: US 2015/0277919 A13 Dec 2015
Granted: 31 Oct 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 9/3013
Organisation of register space, e.g. banked or distributed register file: according to data content, e.g. floating-point registers, address registers
G06F 9/30098
Arrangements for executing machine instructions, e.g. instruction decode: register arrangements
G06F 9/30145
Arrangements for executing machine instructions, e.g. instruction decode: instruction analysis, e.g. decoding, instruction word fields
G06F 9/30189
Instruction operation extension or modification: according to execution mode, e.g. mode flag

Family

Application14/226,895Parent of this continuation · filed 27 Mar 2014
US 2015/0347132 A1Pre-grant publication · published 3 Dec 2015
US 2015/0277919 A1Published application
US 9,804,846 B2Related patent
US 9,804,847 B2This patent

From the US filing history. Foreign family members aren’t listed.